Patents by Inventor Li-Che Chen
Li-Che Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9548375Abstract: A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.Type: GrantFiled: September 28, 2016Date of Patent: January 17, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Hsiung-Shih Chang, Manoj Kumar, Jui-Chun Chang, Chia-Hao Lee, Li-Che Chen
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Patent number: 9499399Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.Type: GrantFiled: June 14, 2013Date of Patent: November 22, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
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Patent number: 9502584Abstract: A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.Type: GrantFiled: November 24, 2015Date of Patent: November 22, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Hsiung-Shih Chang, Manoj Kumar, Jui-Chun Chang, Chia-Hao Lee, Li-Che Chen
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Patent number: 9391139Abstract: A top-side contact structure is provided. The top-side contact structure includes a substrate. The substrate includes a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer. The top-side contact structure also includes a first trench and a second trench formed in the second semiconductor layer and respectively extending along a first direction and a second direction. The first trench and the second trench connect to each other at an intersection point. The top-side contact structure also includes an insulating material filling the first trench and the second trench. The top-side contact structure also includes a contact plug formed at the intersection point and directly contacting the first semiconductor layer. A method for fabricating a top-side contact structure is also provided.Type: GrantFiled: September 23, 2015Date of Patent: July 12, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Hsiung-Shih Chang, Jui-Chun Chang, Li-Che Chen
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Publication number: 20140367805Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
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Patent number: 8776363Abstract: A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween.Type: GrantFiled: May 23, 2012Date of Patent: July 15, 2014Assignee: United Microelectronics Corp.Inventors: Chang-Sheng Hsu, Li-Che Chen, Kuo-Yuh Yang, Chia-Wen Lien, Yan-Da Chen
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Patent number: 8742498Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.Type: GrantFiled: November 3, 2011Date of Patent: June 3, 2014Assignee: United Microelectronics Corp.Inventors: Fu-Chun Chien, Ching-Wei Teng, Nien-Chung Li, Chih-Chung Wang, Te-Yuan Wu, Li-Che Chen, Chih-Chun Pu, Yu-Ting Yeh, Kuan-Wen Lu
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Publication number: 20130312246Abstract: A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Inventors: Chang-Sheng Hsu, Li-Che Chen, Kuo-Yuh Yang, Chia-Wen Lien, Yan-Da Chen
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Patent number: 8587078Abstract: A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.Type: GrantFiled: April 6, 2010Date of Patent: November 19, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Tzung-Han Tan, Hui-Min Wu, Tzung-I Su
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Patent number: 8553911Abstract: A diaphragm of an MEMS electroacoustic transducer including a first axis-symmetrical pattern layer is provided. Because the layout of the first axis-symmetrical pattern layer can match the pattern of the sound wave, the vibration uniformity of the diaphragm can be improved.Type: GrantFiled: November 1, 2012Date of Patent: October 8, 2013Assignee: United Microelectronics Corp.Inventor: Li-Che Chen
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Patent number: 8546739Abstract: A manufacturing method of a wafer level chip scale package of an image-sensing module is provided. The method includes providing a wafer having a plurality of die regions, and a plurality of sensing units is formed on a surface of the wafer in each die region. A plurality of lens units is formed on the sensing units, wherein each lens unit includes a lens and an edge wall that are integrally formed. A light-shielding film is also formed on a surface of at least one edge wall of at least one lens units. A dicing process is then performed on the wafer to form a plurality of image sensor chips.Type: GrantFiled: August 13, 2009Date of Patent: October 1, 2013Inventors: Min-Chih Hsuan, Tsung-Hsi Ko, Li-Che Chen
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Patent number: 8536709Abstract: A wafer with a eutectic bonding carrier and a method of manufacturing the same are disclosed, wherein the wafer comprises a thinned wafer, a eutectic bonding layer formed on the backside of said thinned wafer, a eutectic bonding carrier attached on said eutectic bonding layer, and a plurality of openings formed at the active side of said thinned wafer and exposing said eutectic bonding layer on the backside of said thinned wafer.Type: GrantFiled: June 25, 2012Date of Patent: September 17, 2013Assignee: United Microelectronics Corp.Inventors: Chang-Sheng Hsu, Kuo-Yuh Yang, Li-Che Chen, Yan-Da Chen, Chia-Wen Lien
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Patent number: 8502382Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.Type: GrantFiled: April 30, 2012Date of Patent: August 6, 2013Assignee: United Microelectronics Corp.Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
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Publication number: 20130113048Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Fu-Chun CHIEN, Ching-Wei Teng, Nien-Chung Li, Chih-Chung Wang, Te-Yuan Wu, Li-Che Chen, Chih-Chun Pu, Yu-Ting Yeh, Kuan-Wen Lu
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Patent number: 8368153Abstract: A wafer level package of micro electromechanical system (MEMS) microphone includes a substrate, a number of dielectric layers stacked on the substrate, a MEMS diaphragm, a number of supporting rings and a protective layer. The MEMS diaphragm is disposed between two adjacent dielectric layers. A first chamber is between the MEMS diaphragm and the substrate. The supporting rings are disposed in some dielectric layers and stacked with each other. An inner diameter of the lower supporting ring is greater than that of the upper supporting ring. The protective layer is disposed on the upmost supporting ring and covers the MEMS diaphragm. A second chamber is between the MEMS diaphragm and the protective layer. The protective layer defines a number of first through holes for exposing the MEMS diaphragm. The wafer level package of MEMS microphone has an advantage of low cost.Type: GrantFiled: April 8, 2010Date of Patent: February 5, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Hsin Huang, Li-Che Chen, Ming-I Wang, Bang-Chiang Lan, Hui-Min Wu, Tzung-I Su
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Patent number: 8363859Abstract: A microelectromechanical system microphone package structure includes a base plate and a plurality of chips is provided. The plurality of chips are disposed on the base plate, wherein an active area of each of the chips is disposed with a microelectromechanical system microphone structure, each of the active areas comprises a normal line, and the normal lines of the chips are unparallel and nonorthogonal to each other.Type: GrantFiled: April 13, 2012Date of Patent: January 29, 2013Assignee: United Microelectronics Corp.Inventor: Li-Che Chen
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Patent number: 8345895Abstract: A diaphragm of an MEMS electroacoustic transducer including a first axis-symmetrical pattern layer is provided. Because the layout of the first axis-symmetrical pattern layer can match the pattern of the sound wave, the vibration uniformity of the diaphragm can be improved.Type: GrantFiled: July 25, 2008Date of Patent: January 1, 2013Assignee: United Microelectronics Corp.Inventor: Li-Che Chen
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Publication number: 20120205808Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.Type: ApplicationFiled: April 30, 2012Publication date: August 16, 2012Inventors: Bang-Chiang Lan, Ming-I Wang, Hui-Min Wu, Min Chen, Chien-Hsin Huang, Tzung-I Su, Chao-An Su, Tzung-Han Tan, Li-Che Chen, Meng-Jia Lin
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Publication number: 20120193735Abstract: A microelectromechanical system microphone package structure includes a base plate and a plurality of chips is provided. The plurality of chips are disposed on the base plate, wherein an active area of each of the chips is disposed with a microelectromechanical system microphone structure, each of the active areas comprises a normal line, and the normal lines of the chips are not parallel to each other.Type: ApplicationFiled: April 13, 2012Publication date: August 2, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventor: Li-Che CHEN
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Patent number: 8208662Abstract: A microelectromechanical system microphone structure including a substrate, a first device and at least one second device is provided. The first device is disposed on the substrate and including a first upper electrode and a first lower electrode disposed between the first upper electrode and the substrate. The second device is disposed on the substrate, surrounding the first device and including a second upper electrode and a second lower electrode disposed between the second upper electrode and the substrate. The second upper electrode includes a plurality of first conductive layers and first plugs. The first conductive layers are arranged in steps, and the first plug is disposed between the adjacent first conductive layers. The second lower electrode includes a plurality of second conductive layers and a plurality of second plugs. The second conductive layers are arranged in steps, and the second plug is disposed between the adjacent second conductive layers.Type: GrantFiled: September 16, 2008Date of Patent: June 26, 2012Assignee: United Microelectronics Corp.Inventor: Li-Che Chen