Abstract: A switching circuit includes a normally-on switch, a normally-off switch, a current compensating unit and a current sharing unit. Each of the normally-on switch and the normally-off switch include a first terminal, a second terminal and a control terminal respectively. The first terminal of the normally-off switch is connected to the second terminal of the normally-on switch. The second terminal of the normally-off switch is connected to the control terminal of the normally-on switch. The current compensating unit is connected to the normally-on switch and configured to generate a compensating current when a leakage current of the normally-on switch is smaller than the leakage current of the normally-off switch. The current sharing unit is connected to the normally-off switch and configured to share the leakage current of the normally-on switch when the leakage current of the normally-on switch is larger than the leakage current of the normally-off switch.

Abstract: A semiconductor device includes an element layer, plural source electrodes, plural drain electrodes, plural gate electrodes, a source bus bar, a drain bus bar, a first gate bus bar, and a second gate bus bar. The source electrodes, the drain electrodes, and the gate electrodes are disposed on the element layer and extend along a first direction. The gate electrodes are respectively disposed between the source and drain electrodes. The source and drain bus bars and the first and second gate bus bars extend along a second direction interlaced with the first direction. The source bus bar and the drain bus bar are electrically connected to the source electrodes and the drain electrodes, respectively. The first and second gate bus bars are connected to the gate electrodes. The first bus bar is disposed at one end of the source electrodes. The source electrode crosses the second gate bus bar.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A switching circuit includes a normally-on switch, a normally-off switch, a current compensating unit and a current sharing unit. Each of the normally-on switch and the normally-off switch include a first terminal, a second terminal and a control terminal respectively. The first terminal of the normally-off switch is connected to the second terminal of the normally-on switch. The second terminal of the normally-off switch is connected to the control terminal of the normally-on switch. The current compensating unit is connected to the normally-on switch and configured to generate a compensating current when a leakage current of the normally-on switch is smaller than the leakage current of the normally-off switch. The current sharing unit is connected to the normally-off switch and configured to share the leakage current of the normally-on switch when the leakage current of the normally-on switch is larger than the leakage current of the normally-off switch.

Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a substrate and an active layer on the substrate. A gate electrode is disposed on the active layer. A first electrode and a second electrode are disposed on the active layer, on opposite sides of the gate electrode. A first metal pattern is coupled to the first electrode. A second metal pattern is coupled to the second electrode. A first insulating layer is disposed on the first and second metal patterns. A third metal pattern covers the first insulating layer, coupled to the second metal pattern. An interface between the third metal pattern and the first insulating layer is a substantially planar surface.

Abstract: A semiconductor device includes an active layer, source electrodes, drain electrodes, gate electrodes, a first dielectric layer, source trace, first source vias, a second dielectric layer, a source pad, and second source vias. The first dielectric layer covers the source electrodes, the drain electrodes, and the gate electrodes. The source traces are disposed on the first dielectric layer, are electrically connected to the source electrodes, and are covered by the second dielectric layer. The source pad is disposed on the second dielectric layer, and includes a first source trunk, a first source branch, and a source sub-branch. The first source branch is protruded from the first source trunk and is electrically connected to one of the drain traces through the second source vias. The source sub-branch is protruded from the first source branch and is electrically connected one of the source electrodes through the third source vias.

Abstract: A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode. The first electrode and the edge of the gate electrode facing the first electrode are regular polygons, and have the same center.

Abstract: A light emitting semiconductor element includes at least two electrically conductive units, at least a light emitting semiconductor die and a light transmitting layer. A groove is located between the two electrically conductive units. The light emitting semiconductor die is cross over the electrically conductive units. The light transmitting layer covers the light emitting semiconductor and partially fills within the groove for linking the electrically conductive units.

Abstract: A semiconductor device package includes a substrate, a transistor, and a lead frame disposed on a side of the substrate opposite to the transistor. The transistor is disposed on the substrate, and includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, a first drain pad, a source plug, and a drain plug. The source and the drain electrodes are disposed on the active layer. An orthogonal projection of the source electrode on the active layer forms a source region. The first insulating layer covers at least a portion of the source electrode and at least a portion of the drain electrode. The first source pad and the first drain pad are disposed on the first insulating layer. An orthogonal projection of the first source pad on the active layer forms a source pad region overlaps the drain region.

Abstract: A semiconductor device package includes a substrate, a transistor, and a lead frame disposed on a side of the substrate opposite to the transistor. The transistor is disposed on the substrate, and includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, a first drain pad, a source plug, and a drain plug. The source and the drain electrodes are disposed on the active layer. An orthogonal projection of the source electrode on the active layer forms a source region. The first insulating layer covers at least a portion of the source electrode and at least a portion of the drain electrode. The first source pad and the first drain pad are disposed on the first insulating layer. An orthogonal projection of the first source pad on the active layer forms a source pad region overlaps the drain region.

Abstract: A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a circle or polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode.

Abstract: An illumination apparatus includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. The light emitted from the third light-emitting device is selectively mixed with the light emitted from the first light-emitting device or the second light-emitting device to form a white light having a chromaticity coordinate point substantially located on a Black Body Locus. A color of the light emitted from the third light-emitting device is determined by linear relationships between chromaticity coordinate points corresponding to wavelengths of the lights emitted form the first light-emitting device and the second light-emitting device and corresponding to a color temperature of the white light. A method for generating a white light is also disclosed herein.

Abstract: A light emitting element including an epitaxy layer, at least one first electrode, at least one second electrode, a first bonding pad and a second bonding pad. The epitaxy layer includes in sequence a first semiconductor layer, an active layer and a second semiconductor layer, and the first semiconductor layer has an exposed portion exposed from the second semiconductor layer and the active layer. The first electrode is disposed at the exposed portion. The second electrode is disposed at the second semiconductor layer. The first bonding pad is connected with the first electrode. The second bonding pad is connected with the second electrode. Two light emitting elements with different structures and the light emitting module utilizing the light emitting elements mentioned above are also disclosed.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode. The first electrode and the edge of the gate electrode facing the first electrode are regular polygons, and have the same center.

Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a substrate and an active layer on the substrate. A gate electrode is disposed on the active layer. A first electrode and a second electrode are disposed on the active layer, on opposite sides of the gate electrode. A first metal pattern is coupled to the first electrode. A second metal pattern is coupled to the second electrode. A first insulating layer is disposed on the first and second metal patterns. A third metal pattern covers the first insulating layer, coupled to the second metal pattern. An interface between the third metal pattern and the first insulating layer is a substantially planar surface.

Abstract: A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a circle or polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode.

Abstract: A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.

Abstract: A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.