Patents by Inventor Li-Han Hsu
Li-Han Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11470720Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.Type: GrantFiled: March 1, 2021Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
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Publication number: 20220268400Abstract: A communication apparatus and a bracket device thereof are provided. The bracket device includes a base, a rotary shaft, a connecting member, and an elastic member. The base includes a bottom portion, a connecting portion, and a base engaging portion. The rotary shaft is rotatably disposed in the connecting portion and includes a base wall and a connecting section. The connecting member connects to the rotary shaft. The elastic member includes a body and an elastic member engaging portion. The body connects to the base wall of the rotary shaft, and the elastic member engaging portion is positioned at the body. In an engagement state, the elastic member engaging portion is engaged to the base engaging portion.Type: ApplicationFiled: July 12, 2021Publication date: August 25, 2022Inventors: LAN-CHUN YANG, CHUN-HUNG HUANG, LI-HAN HSU, YI-CHIEH LIN
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Publication number: 20220093526Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
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Patent number: 11195802Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.Type: GrantFiled: June 5, 2020Date of Patent: December 7, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
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Publication number: 20210305122Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.Type: ApplicationFiled: March 31, 2020Publication date: September 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
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Publication number: 20210267363Abstract: A rack assembly has two support frames and at least one shelf that are secured to the support frames by connecting assemblies. Each connecting assembly comprises a well secured to a medial surface of each vertical tube of the support frame, and a hook that extends from each end of each shelf, with each hook having an opening extending therethrough. The connecting assembly also includes a connector that is seated inside each well, each connector having a top plate that has an elongated opening, the connector also having a body that is sized and configured to fit inside a well, the body defining two wings with a space between the wings, and wherein each wing has a bump positioned in the center of the inner surface of each wing that faces the space. Each hook is inserted through the elongated opening of a corresponding connector with the bump on each wing fitted inside the opening of the hook to retain the hook inside the body of the connector.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Applicant: Seville Classics Inc.Inventor: Li-Han Hsu
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Patent number: 11069625Abstract: A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.Type: GrantFiled: December 24, 2018Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu
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Publication number: 20210217682Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.Type: ApplicationFiled: April 1, 2021Publication date: July 15, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chia Chiu, Li-Han Hsu
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Publication number: 20210193618Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.Type: ApplicationFiled: March 9, 2021Publication date: June 24, 2021Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20210185810Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.Type: ApplicationFiled: March 1, 2021Publication date: June 17, 2021Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
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Patent number: 11018088Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.Type: GrantFiled: June 10, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11013318Abstract: A rack assembly has two support frames and at least one shelf that are secured to the support frames by connecting assemblies. Each connecting assembly comprises a well secured to a medial surface of each vertical tube of the support frame, and a hook that extends from each end of each shelf, with each hook having an opening extending therethrough. The connecting assembly also includes a connector that is seated inside each well, each connector having a top plate that has an elongated opening, the connector also having a body that is sized and configured to fit inside a well, the body defining two wings with a space between the wings, and wherein each wing has a bump positioned in the center of the inner surface of each wing that faces the space. Each hook is inserted through the elongated opening of a corresponding connector with the bump on each wing fitted inside the opening of the hook to retain the hook inside the body of the connector.Type: GrantFiled: May 27, 2020Date of Patent: May 25, 2021Assignee: Seville Classics Inc.Inventor: Li-Han Hsu
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Patent number: 10971425Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.Type: GrantFiled: April 3, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chia Chiu, Li-Han Hsu
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Publication number: 20210098391Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.Type: ApplicationFiled: June 5, 2020Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
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Patent number: 10950577Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.Type: GrantFiled: October 23, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 10939551Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.Type: GrantFiled: November 29, 2018Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
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Patent number: 10867900Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.Type: GrantFiled: November 15, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
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Publication number: 20200343193Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
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Publication number: 20200281352Abstract: A rack assembly has two support frames and at least one shelf that are secured to the support frames by connecting assemblies. Each connecting assembly comprises a well secured to a medial surface of each vertical tube of the support frame, and a hook that extends from each end of each shelf, with each hook having an opening extending therethrough. The connecting assembly also includes a connector that is seated inside each well, each connector having a top plate that has an elongated opening, the connector also having a body that is sized and configured to fit inside a well, the body defining two wings with a space between the wings, and wherein each wing has a bump positioned in the center of the inner surface of each wing that faces the space. Each hook is inserted through the elongated opening of a corresponding connector with the bump on each wing fitted inside the opening of the hook to retain the hook inside the body of the connector.Type: ApplicationFiled: May 27, 2020Publication date: September 10, 2020Applicant: Seville Classics Inc.Inventor: Li-Han Hsu
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Patent number: 10714426Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.Type: GrantFiled: August 27, 2018Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin