Patents by Inventor Li-Han Hsu

Li-Han Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10667604
    Abstract: A rack assembly has two support frames and at least one shelf that are secured to the support frames by connecting assemblies. Each connecting assembly comprises a well secured to a medial surface of each vertical tube of the support frame, and a hook that extends from each end of each shelf, with each hook having an opening extending therethrough. The connecting assembly also includes a connector that is seated inside each well, each connector having a top plate that has an elongated opening, the connector also having a body that is sized and configured to fit inside a well, the body defining two wings with a space between the wings, and wherein each wing has a bump positioned in the center of the inner surface of each wing that faces the space. Each hook is inserted through the elongated opening of a corresponding connector with the bump on each wing fitted inside the opening of the hook to retain the hook inside the body of the connector.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 2, 2020
    Assignee: Seville Classics, Inc
    Inventor: Li-Han Hsu
  • Patent number: 10629537
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20200105640
    Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.
    Type: Application
    Filed: April 3, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chia Chiu, Li-Han Hsu
  • Publication number: 20200083156
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Publication number: 20200058616
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190380485
    Abstract: A rack assembly has two support frames and at least one shelf that are secured to the support frames by connecting assemblies. Each connecting assembly comprises a well secured to a medial surface of each vertical tube of the support frame, and a hook that extends from each end of each shelf, with each hook having an opening extending therethrough. The connecting assembly also includes a connector that is seated inside each well, each connector having a top plate that has an elongated opening, the connector also having a body that is sized and configured to fit inside a well, the body defining two wings with a space between the wings, and wherein each wing has a bump positioned in the center of the inner surface of each wing that faces the space. Each hook is inserted through the elongated opening of a corresponding connector with the bump on each wing fitted inside the opening of the hook to retain the hook inside the body of the connector.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Applicant: Seville Classics Inc.
    Inventor: Li-Han Hsu
  • Patent number: 10510654
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 10504751
    Abstract: Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Cheng-Hsien Hsieh, Li-Han Hsu, Lai Wei Chih
  • Patent number: 10475768
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190295955
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10398224
    Abstract: A rack assembly has two support frames and at least one shelf that are secured to the support frames by connecting assemblies. Each connecting assembly comprises a well secured to a medial surface of each vertical tube of the support frame, and a hook that extends from each end of each shelf, with each hook having an opening extending therethrough. The connecting assembly also includes a connector that is seated inside each well, each connector having a top plate that has an elongated opening, the connector also having a body that is sized and configured to fit inside a well, the body defining two wings with a space between the wings, and wherein each wing has a bump positioned in the center of the inner surface of each wing that faces the space. Each hook is inserted through the elongated opening of a corresponding connector with the bump on each wing fitted inside the opening of the hook to retain the hook inside the body of the connector.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 3, 2019
    Assignee: Seville Classics, Inc
    Inventor: Li-Han Hsu
  • Patent number: 10319681
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10290584
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190131249
    Abstract: A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.
    Type: Application
    Filed: December 24, 2018
    Publication date: May 2, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hsien HSIEH, Li-Han HSU, Wei-Cheng WU, Hsien-Wei CHEN, Der-Chyang YEH, Chi-Hsi WU
  • Publication number: 20190122975
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Publication number: 20190115299
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 18, 2019
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20190098756
    Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 10163805
    Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu
  • Patent number: D840728
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 19, 2019
    Assignee: Seville Classics, Inc.
    Inventor: Li-Han Hsu
  • Patent number: D843792
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 26, 2019
    Assignee: Seville Classics Inc.
    Inventor: Li-Han Hsu