Abstract: The invention relates to a sample holder assembly (1) for microscopy comprising at least the following components: A first member (10) having a first opening (14) on a first side of the first member (10), and a circumferential wall portion (12) having an inward facing side (12-1) that faces toward the first volume (V1) and an outward facing side (12-2) opposite the inward facing side (12-1); A second member (20) having a first opening (24) at a first side of the second member (20), and a circumferential wall portion (22) having an inward facing side (22-1) facing toward the second volume (V2), wherein a shape of the outward facing side (12-2) of the wall portion (12) of the first member (10) is complementary to the inward facing side (22-1) of the wall portion (22) of the second member (20), such that the wall portion (12) of the first member (10) can be inserted in the second volume (V2), such that the first volume (V1) is at least partially comprised by the second volume (V2); A transparent membrane (30) ha

Abstract: Devices and method for forming a chip package structure including a package substrate, a fan-out package attached to the package substrate, a first adhesive layer attached to a top surface of the package substrate, a beveled stiffener structure attached to the package substrate and surrounding the fan-out package, the beveled stiffener structure comprising at least one tapered sidewall, in which a first width of a top portion of the beveled stiffener structure along the at least one tapered sidewall is greater than a second width of a bottom portion of the beveled stiffener structure along the at least one tapered sidewall, and in which the bottom portion is in contact with a top surface of the first adhesive layer.

Abstract: Methods and apparatus for etching a substrate in a plasma etch chamber are provided. In one example, the method includes exposing a substrate disposed on a substrate supporting surface of a substrate support to a plasma within a processing chamber, and applying a voltage waveform to an electrode disposed in the substrate support while the substrate is exposed to the plasma during a plurality of macro etch cycles. Each macro etch cycle includes a first macro etch period and a second macro etch period. The macro etch period includes a plurality of micro etch cycles. Each micro etch cycle has a bias power on (BPON) period and a bias power off (BPOFF) period, wherein a duration of the BPON period being less than a duration of the BPOFF period. Bias power is predominantly not applied to the electrode during the second macro etch period.

Abstract: According to a first aspect of the present invention, there is provided a chip processing self-service kiosk comprising: a chip slot; a chip sensor; and a mechanical arrangement disposed downstream of the chip slot, the mechanical arrangement configured to allow received chips from the chip slot to be stacked in an orientation where the received chips are countable by the chip sensor.

Abstract: A package includes a first package component, which includes a bottom dielectric layer, a micro-bump protruding below the bottom dielectric layer, and a metal pillar protruding below the bottom dielectric layer. The metal pillar has a top width and a bottom width greater than the top width. The package further includes a die underlying and bonding to the micro-bump, a solder region underlying and joining to a bottom surface of the metal pillar, and a second package component underlying the first package component. The second package component includes a conductive feature underlying and joining to the solder region.

Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an interposer, a substrate, and an integrated circuit device between the interposer and the substrate. The integrated circuit device, which may correspond to an integrated passive device, is attached to the interposer within a cavity of the interposer. Attaching the integrated circuit device within the cavity of the interposer creates a clearance between the integrated circuit device and the substrate. In this way, a likelihood of the integrated circuit device contacting the substrate during a bending and/or a deformation of the semiconductor package is reduced. By reducing the likelihood of such contact, damage to the integrated circuit device and/or the substrate may be avoided to increase a reliability and/or yield of the semiconductor package.

Abstract: A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer. The die is electrically bonded to the interposer and disposed over the interconnection structure. The conductive terminal is connected to the interposer and the die via a conductive bump. In order to effectively avoid cold joint issues, round or rectangular polyimide structures are first disposed under the bumps to structurally support the bump and sufficiently increase bump height for improved electrical connection and long term reliability of the package structure.

Abstract: Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The redistribution structure includes a first redistribution structure portion physically and electrically connected to the first semiconductor die, a second redistribution structure portion physically and electrically connected to the second semiconductor die, and a dummy bump region positioned between and electrically isolated from the first redistribution structure portion and the second redistribution structure portion.

Abstract: Semiconductor packages and methods of fabricating semiconductor packages include bonding structures on a surface of an interposer having non-uniform height dimensions in different regions of the interposer. A plurality of solder connections may contact the pillars and electrically connect the respective pillars of the interposer to corresponding bonding structures on a package substrate. The variation in the heights of the pillars in different regions of the interposer may compensate for warping of the interposer and improve the reliability of the electrical connections between the interposer and the package substrate.

Abstract: Some implementations herein describe a semiconductor package. The semiconductor package, which may correspond to a high-performance computing semiconductor package, includes an interposer. The interposer includes tapered interconnect structures formed using a laser plug process. The tapered interconnect structures may include a length that is lesser relative to a length of the column-shaped interconnect structures formed using a through-silicon via process. Such a length reduces a thickness of the interposer and reduces a length of electrical connections through the interposer. In this way, a signal integrity may be increased and parasitics of the semiconductor package including the tapered interconnect structures may be reduced to increase a performance of the semiconductor package. Additionally, the reduced thickness of the interposer may reduce an overall thickness of the semiconductor package to save space consumed by the semiconductor package in a computing system.

Abstract: A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.

Abstract: A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring.

Abstract: Devices and method for forming a chip package structure including at least one semiconductor die attached to a redistribution structure, a molding compound die frame laterally surrounding the at least one semiconductor die, and a first underfill material portion located between the redistribution structure and the at least one semiconductor die and contacting sidewalls of the at least one semiconductor die and sidewalls of the molding compound die frame. The first underfill material portion may include at least one cut region, in which the first underfill material portion may include a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Abstract: A semiconductor structure and methods for forming the same including a package comprising at least one semiconductor die, a redistribution structure comprising bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure, a substrate package comprising chip-side bonding pads and at least one substrate trench, in which the at least one substrate trench extends vertically below a top surface of the substrate package in a cross-section view, solder material portions bonded to the chip-side bonding pads and the bonding pads, and a second underfill material portion laterally surrounding the solder material portions and dispensed within the at least one substrate trench.

Abstract: The invention relates generally to the field of wound healing. In one embodiment is a method for generating a delayed wound model in an animal, the method comprising contacting a wound with a composition comprising an electrospun scaffold, wherein the scaffold is made from 80% PCL and 20% rat tail collagen and has been soaked in a biofilm conditioned media from Staphylococcus aureus or a small molecular drug FK866.

Abstract: A method for forming a chip package structure is provided. The method includes forming a dielectric layer over a redistribution structure. The redistribution structure includes a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The method includes forming a first conductive bump structure and a shield bump structure over the dielectric layer. The first conductive bump structure is electrically connected to the wiring layers, and the shield bump structure is electrically insulated from the wiring layers. The method includes bonding a first chip structure to the redistribution structure through the first conductive bump structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure extends across a first sidewall of the shield bump structure.

Abstract: A keyboard key device includes a keycap and a substrate unit. The substrate unit includes a light-emitting component, a light guide plate, and a light transmission plate. The light guide plate has first and second end surfaces, and at least one light-condensing hole. The first end surface is formed with an uneven microstructure for diffuse reflection of light rays. The light transmission plate has first and second side surfaces, and an outer reflective layer coated on the second side surface. A portion of light rays emitted from the light-emitting component and into the light transmission plate pass through the outer reflective layer, and the remainder of the light rays are reflected by the outer reflective layer.