Patents by Inventor Li Ling

Li Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705406
    Abstract: A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chen Lai, Chin-Hua Wang, Ming-Chih Yew, Li-Ling Liao, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230223328
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Inventors: Li-Ling Liao, Ming-Chih Yew, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11673831
    Abstract: A method for preparing optical fibers formed with high-particle-coated porous polymeric outer coating layer is provided. The method includes preparing a coating suspension solution by dispersing a plurality of particles into an organic solvent system, immersing one or more optical fibers into the coating suspension solution, removing the one or more optical fibers from the coating suspension solution to form high-particle-coated porous polymeric outer coating layer after drying. Concentrations and compositions of the particles in the coating suspension solution, concentrations and compositions of the organic solvent system, the period of time of immersing, or the external environment are adjusted such that the optical fibers is formed with high-particle-coated polymeric outer coating layers having desirable coating masses, coating thicknesses, or coating morphologies.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: June 13, 2023
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Li Ling, Zihang Cheng, Chii Shang
  • Patent number: 11610835
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Ling Liao, Ming-Chih Yew, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230063295
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a package substrate, a first die, and a stiffener ring. The first die is disposed on the package substrate and has a first sidewall and a second sidewall opposite to each other. The stiffener ring is disposed on the package substrate to surround the first die. The stiffener ring has an inner sidewall facing the first die, and the inner sidewall at least has a slant sidewall facing the first sidewall of the first die.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Chia Yang, Shu-Shen Yeh, Li-Ling Liao, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230069794
    Abstract: A microscope system (100) configured to record images in at least a first and a second imaging mode (501, 502), comprising: An objective (1) collecting light (201) from a sample (11), An illumination module coupled to the objective, A first reimaging objective (5) generating an intermediate image of the sample and a second reimaging objective (6) that relays the intermediate image onto a detection module, An evaluation module (200) comprising a machine learning method (DL), trained with a first and a second set of images of the same sample, wherein the first and second set has been acquired in the first (501) and second imaging mode (502), respectively, wherein upon acquisition of an image (400) in the second imaging mode (502) the trained machine learning method (DL) outputs a restored image (401) that comprises fewer aberrations than the image (400) acquired in the second imaging mode (52, 53, 57).
    Type: Application
    Filed: February 17, 2021
    Publication date: March 2, 2023
    Applicant: CHARITÉ-UNIVERSITÄTSMEDIZIN BERLIN
    Inventors: Yang LI-LING, Conrad CHRISTIAN, Ten FOO WEI, Eils ROLAND
  • Publication number: 20230063251
    Abstract: A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling Liao, Ming-Chih Yew, Che-Chia Yang, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230066598
    Abstract: A package structure is provided. The package structure includes a redistribution structure over a substrate, a semiconductor die over the redistribution structure and electrically coupled to the substrate, and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die. The underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Po-Chen LAI, Ming-Chih YEW, Li-Ling LIAO, Chin-Hua WANG, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20230069311
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Shu-Shen YEH, Po-Chen LAI, Che-Chia YANG, Li-Ling LIAO, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20230057145
    Abstract: A plasma treatment chamber comprises one or more sidewalls and a support surface within the sidewalls holds a workpiece. An array of individual gas injectors is distributed about the sidewalls. Pump ports are along the sidewalls to eject gas from the chamber. Aa etch rate uniformity of a material on the workpiece is controlled by: using the array gas injectors to inject one or more gas flows in across the workpiece; injecting a first gas flow from a first set of adjacent individual gas injectors to etch the materials on the workpiece; and simultaneously injecting a second gas flow from remaining gas injectors. The second gas flow either dilutes the first gas flow to reduce an area on the workpiece having a faster etch rate, or acts as an additional etchant to increase the etch rate in the area of the workpiece having the faster etch rate.
    Type: Application
    Filed: June 3, 2022
    Publication date: February 23, 2023
    Inventors: DAISUKE SHIMIZU, Kenji Takeshita, James D. Carducci, Li Ling, Hikaru Watanabe, Kenneth S. Collins, Michael R. Rice
  • Publication number: 20230039563
    Abstract: A heat-shrinkable polyester film includes at least one polyester material made of at least one polyester forming composition which includes a dibasic carboxylic mixture and a diol mixture. The heat-shrinkable polyester film has a heat shrinkage rate of not lower than 25% in a shrinkage direction, which is measured by immersing the heat-shrinkable polyester film in hot water at 65° C. for 10 seconds. A method for producing the heat-shrinkable polyester film is also disclosed.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 9, 2023
    Inventors: Hsin-Yu LIU, Li-Ling CHANG, Yow-An LEU
  • Publication number: 20230045508
    Abstract: Disclosed herein are a heat-shrinkable polyester label film and a preparation method thereof. The label film has a shrinkage force not lower than 5.5 N in at least one shrinkage direction after immersing the heat-shrinkable polyester label film in water at 55° C. for 30 seconds, and a heat shrinkage rate of not lower than 50% in the shrinkage direction after immersing the heat-shrinkable polyester label film in water at 55° C. for 240 seconds.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 9, 2023
    Inventors: Yi-Fen CHEN, Yow-An LEU, Li-Ling CHANG
  • Publication number: 20230017688
    Abstract: A method for forming a chip package structure is provided. The method includes forming a dielectric layer over a redistribution structure. The redistribution structure includes a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The method includes forming a first conductive bump structure and a shield bump structure over the dielectric layer. The first conductive bump structure is electrically connected to the wiring layers, and the shield bump structure is electrically insulated from the wiring layers. The method includes bonding a first chip structure to the redistribution structure through the first conductive bump structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure extends across a first sidewall of the shield bump structure.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Inventors: Po-Chen LAI, Chin-Hua WANG, Ming-Chih YEW, Chia-Kuei HSU, Li-Ling LIAO, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20220406729
    Abstract: A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Po-Chen LAI, Chin-Hua WANG, Ming-Chih YEW, Li-Ling LIAO, Tsung-Yen LEE, Po-Yao LIN, Shin-Puu JENG
  • Patent number: 11516506
    Abstract: A method, performed by a digital device, for processing an image service according to the present document comprises the steps of: receiving image information; decoding a first image on the basis of the image information; processing the decoded first image to be displayed on a first area of a display screen; and processing a second image to be displayed on a second area of the display screen.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 29, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: Li Ling, Jin Heo, Seunghwan Kim
  • Publication number: 20220319909
    Abstract: The present disclosure provides a method for manufacturing a semiconductor memory device. Because the present method includes applying a dopant-implanted layer on a semiconductor memory substrate before growing a silicon nitride layer on the substrate, the silicon nitride layer can be grown at an increased rate. The present disclosure avoids a problem encountered in the prior art wherein a seam having a greater length contacts an edge of a contact plug of a semiconductor memory device. Hence, a leakage problem at subsequent operations of semiconductor manufacture can be avoided, and the product yield can be significantly improved.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 6, 2022
    Inventors: CHING-LIANG KAO, WEN-CHIEH WU, LI-LING KE
  • Publication number: 20220293356
    Abstract: A keyboard key device includes a keycap and a substrate unit. The substrate unit includes a light-emitting component, a light guide plate, and a light transmission plate. The light guide plate has first and second end surfaces, and at least one light-condensing hole. The first end surface is formed with an uneven microstructure for diffuse reflection of light rays. The light transmission plate has first and second side surfaces, and an outer reflective layer coated on the second side surface. A portion of light rays emitted from the light-emitting component and into the light transmission plate pass through the outer reflective layer, and the remainder of the light rays are reflected by the outer reflective layer.
    Type: Application
    Filed: July 27, 2021
    Publication date: September 15, 2022
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Chih-Hsien WU, Shih-Pin LIN, Li-Ling HUANG, Hsiang-Yi CHEN
  • Patent number: 11396599
    Abstract: A heat-shrinkable polyester film is made of a polyester resin composition, and has first and second crystal melting peaks at a respective one of first and second melting temperatures determined via differential scanning calorimetry. The heat-shrinkable polyester film further has a melting enthalpy in a range of larger than 0 J/g and at most 7 J/g which is calculated via integration of an area below the second crystal melting peak. The polyester resin composition includes a first polyester resin having a glass transition temperature ranging from 40° C. to 80° C., and a second polyester resin having a crystal melting temperature ranging from 220° C. to 250° C. and a melting enthalpy ranging from 40 J/g to 60 J/g.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 26, 2022
    Assignee: FAR EASTERN NEW CENTURY CORPORATION
    Inventors: Yow-An Leu, Li-Ling Chang, Chun-Chia Hsu
  • Patent number: 11358619
    Abstract: An inclined handcart includes a frame including two hook-shaped rearward inclined members at two sides respectively; two wheel mounts secured to bottoms of two front corners of the frame respectively; two rear wheels rotatably secured to two rear ends of the rearward inclined members respectively; two front casters rotatably secured to the wheel mounts respectively; a plurality of links interconnecting the rearward inclined members; two plate members mounted on the rearward inclined members respectively, each plate member having a shoulder extending inward; and a first limit board extending from the rear ends of the rearward inclined members.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 14, 2022
    Inventors: Li-Ling Yang, Chen Huan Hsieh
  • Patent number: D976030
    Type: Grant
    Filed: May 22, 2022
    Date of Patent: January 24, 2023
    Inventor: Li Ling