Patents by Inventor Li Yang

Li Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11937306
    Abstract: A system information transmission method, a terminal and a network device are provided. The method includes: receiving request information for requesting target Other System Information sent by a terminal; configuring a random access message 2 or a random access message 4 for the terminal based on the request information; and sending the random access message 2 or the random access message 4 to the terminal.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 19, 2024
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Li Chen, Xiaodong Yang
  • Patent number: 11937285
    Abstract: Methods and apparatus for interference discovery for simultaneous transmission and reception are provided. In an embodiment, a station (STA) receives a STR request message from an access point (AP). The STA transmits a first STR response message to the AP based on the received STR request message. The STA receives a second STR response message transmitted from a second STA to the AP. The STA determines a received power of the received second STR response message. The STA receives a first trigger message from the AP. The first trigger message indicates a STA role field. The STA transmits interference information to the AP. The interference information is based on the determined received power. The STA role field comprises an indication of at least one or more of a primary STA and a secondary STA. The STA aggregates the interference report with a data transmission to the AP in response to the first trigger message.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: March 19, 2024
    Assignee: Interdigital Patent Holdings, Inc.
    Inventors: Hanqing Lou, Alphan Sahin, Oghenekome Oteri, Li-Hsiang Sun, Xiaofei Wang, Rui Yang
  • Patent number: 11934066
    Abstract: A display device and a manufacturing method thereof, an electronic device, and a light control panel are provided. The display device includes a light control panel and a display liquid crystal panel. The display liquid crystal panel is on a light-emitting side of the light control panel; the light control panel includes a light control region, and the light control region is configured to provide adjusted backlight to the display liquid crystal panel; the display liquid crystal panel includes a display region, and the display region is configured to receive the adjusted backlight to perform display; and a distance between two opposite edges of the light control region in at least one direction is greater than a distance between two opposite edges of the display region in the at least one direction.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: March 19, 2024
    Assignees: HEFEI BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuntian Zhang, Zhou Rui, Peng Jiang, Haipeng Yang, Chunxu Zhang, Zhonghou Wu, Li Tian, Ke Dai
  • Publication number: 20240087861
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
  • Publication number: 20240088034
    Abstract: A microelectronic structure including a first nano device, where the first nano device includes a plurality of transistors. A bottom dielectric isolation located on the backside of each of the plurality of transistors of the first nano device. A separating dielectric layer located on the backside of the bottom dielectric isolation layer, where the separating dielectric layer is a continuous layer on the backside of each of the plurality of transistors of the first nano device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Tsung-Sheng Kang, Tao Li, Ruilong Xie, Chih-Chao Yang
  • Publication number: 20240086730
    Abstract: At least one processor identifies dependency relationships among libraries in a repository of libraries. Using the dependency relationships among libraries, at least one machine learning model can be created that predicts with a confidence value a dependency between a given library and a target library. An L layer tree-like graph can be created, using the dependency relationships among libraries and an application package. L can be configurable. Versions of the libraries to use can be determined by running the at least one machine learning model for each pair of nodes having a dependency relationship in the L layer tree-like graph, the at least one machine learning model identifying the dependency relationship with a confidence value, where pairs of nodes having largest confidence values are selected as the versions of the libraries to use in the application package.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Jin Wang, Lei Gao, A Peng Zhang, Kai Li, Xin Feng Zhu, Geng Wu Yang, Jia Xing Tang, Yan Liu
  • Publication number: 20240083742
    Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li YANG, Kai-Di WU, Ming-Da CHENG, Wen-Hsiung LU, Cheng Jen LIN, Chin Wei KANG
  • Publication number: 20240084369
    Abstract: A digital microfluidic apparatus and a driving method therefor. The digital microfluidic apparatus comprises a digital microfluidic chip (10), a thermal control apparatus (20), and an elastic support apparatus (30). The digital microfluidic chip (10) is provided with a droplet channel (91), and the droplet channel (91) is configured to allow droplets (90) to move therein; the thermal control apparatus (20) is disposed on one side of the digital microfluidic chip (10), and is configured to generate at least two independent and non-interference hot zones in the droplet channel (91), and control the temperature of each hot zone; and the elastic support apparatus (30) is disposed on the side of the thermal control apparatus (20) away from the digital microfluidic chip (10), and is configured to drive the thermal control apparatus (20) to be pasted on the surface of the digital microfluidic chip (10).
    Type: Application
    Filed: July 21, 2022
    Publication date: March 14, 2024
    Inventors: Qiuxu WEI, Wenliang YAO, Yongjia GAO, Bolin FAN, Yingying ZHAO, Le GU, Li YANG
  • Publication number: 20240080918
    Abstract: In a communication method, a session management function network element initiates a procedure of a first operation for a first session; the session management function network element receives a request to establish user-plane resources for the first session from an access and mobility management function network element in a process of performing the first operation; and the session management function network element determines a subsequent procedure based on the first operation.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Inventors: Linping Yang, Xiange Hu, Wen Hu, Li Qiang
  • Publication number: 20240079294
    Abstract: A semiconductor device is provided. The semiconductor device includes a first source/drain of a first semiconductor device, and a second source/drain of a second semiconductor device. The semiconductor device further includes a source/drain contact adjoining a first side of the first source/drain, a frontside via adjoining the source/drain contact, and a backside electric contact adjoining a first side of the second source/drain, wherein the backside electric contact is on a side opposite the source/drain contact, and a conductive alignment region. The device further includes a backside interconnect electrically connected to the conductive alignment region, wherein the backside interconnect is on the same side of the first and second source/drain as the backside electric contact, and an alignment region via electrically connected to the conductive alignment region, wherein the alignment region via is on the same side of the first and second source/drain as the source/drain contact and frontside via.
    Type: Application
    Filed: September 2, 2022
    Publication date: March 7, 2024
    Inventors: Tao Li, Ruilong Xie, Chih-Chao Yang, David Wolpert
  • Publication number: 20240077078
    Abstract: The present disclosure relates to a rotary vane vacuum pump 300 (300?) comprising a gas ballast assembly 330. The gas ballast assembly 330 comprises a gas ballast passage fluidly connected to a stator chamber 212 of the pump 300, a gas ballast valve 334 configured to selectively open and close the gas ballast passage depending on the relative gas pressure across the valve 334, and a gas ballast buffer chamber 360 fluidly connected to the gas ballast passage upstream of the gas ballast valve 343, which is in selective fluid communication with the exterior of the pump 300 (300?). The present disclosure also provides a related method of communicating ballast gas to a rotary vane vacuum pump 300 (300?).
    Type: Application
    Filed: December 23, 2021
    Publication date: March 7, 2024
    Inventors: Li Ouyang, Chuanlei Yang
  • Patent number: 11923373
    Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Bo Tao, Li Wang, Ching-Yang Wen, Purakh Raj Verma, Zhibiao Zhou, Dong Yin, Gang Ren, Jian Xie
  • Patent number: 11920055
    Abstract: A process for producing a barrier composition includes subjecting a siloxane compound having 1 to 3 amino groups and an aqueous solution including water and an alcohol to hydrolysis and first-stage condensation under required conditions, subjecting a first colloidal mixture obtained and an additional alcohol to second-stage condensation, subjecting a second colloidal mixture obtained, which has a particular solid content, to heating under required conditions, and subjecting a cured product obtained to aging under required conditions. A barrier composition produced by the process is also disclosed.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 5, 2024
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Chung-Kuang Yang, Yi-Hsuan Lai, Sheng-Tung Huang, Kun-Li Wang
  • Patent number: 11923041
    Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: March 5, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Mu-Yang Ye, Lu-Ping Kong, Ming-Hung Chang
  • Patent number: 11923199
    Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Patent number: 11917945
    Abstract: An outdoor moving device includes a main body, a first energy storage device, a second energy storage device, and a connection assembly. The first energy storage device is capable of supplying power to the outdoor moving device and includes at least one first energy storage unit. The second energy storage device is capable of supplying power to the outdoor moving device and includes at least one second energy storage unit. The connection assembly is used for mounting the second energy storage device to the main body. The first energy storage device is detachably mounted to the main body, the first energy storage device is detachable from the main body to supply power to another power tool, the first energy storage unit includes a first positive electrode made of a first material, and the second energy storage unit includes a second positive electrode made of a second material.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 5, 2024
    Assignee: Nanjing Chervon Industry Co., Ltd.
    Inventors: Dezhong Yang, Yangzi Liu, Li Li, Ju Li, Changhai Lu
  • Publication number: 20240072001
    Abstract: An integrated circuit (IC) assembly method is provided. The method includes fabricating a first wafer including a first device with a back end of line (BEOL) and first terminals of first and second types at the BEOL and fabricating a second wafer including a second device for back side power delivery network (BSPDN) processing, second terminals of the first type, first vias and second vias. The first and second wafers are bonded at the BEOL to connect the second terminals of the first type to a subset of the first terminals of the first type, the first vias to remaining first terminals of the first type, and the second vias to the first terminals of the second type. A BSPDN is built onto a backside of the second wafer to include first and second BSPDN terminals connected to the first and second vias, respectively.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Tao Li, Ruilong Xie, Chih-Chao Yang, Brent A. Anderson
  • Publication number: 20240068069
    Abstract: Copper-tin-nickel brazing material prepared by alloys recycled from E-waste, preparation method therefor, and system thereof are provided. A preparation method for the copper-tin-nickel brazing material includes the following steps: (a) spreading nano-SiO2 on the bottom of crucible and then adding a crude copper-tin-iron-nickel alloy recycled from E-waste; (b) heating the crucible to melt the crude alloy into a metal liquid so that Zn and Pb in the metal liquid react with the SiO2 to form a slag that floats out; (c) introducing a refining gas to the bottom of metal liquid in step (b), thereby removing the scums or gases formed by Pb, Fe, S, and O in the metal liquid; (d) performing heat-preserving directional solidification on the metal liquid, to bias-aggregate the Fe and Sb at one end and remove the same to obtain a copper-based intermediate alloy; and smelting and powdering the copper-based intermediate alloy.
    Type: Application
    Filed: August 29, 2023
    Publication date: February 29, 2024
    Inventors: Weimin LONG, Tianran DING, Sujuan ZHONG, Li BAO, Junlan HUANG, Jiao YANG, Yuanyuan DONG, Hangyan XUE, Yanhong GUO
  • Patent number: D1017110
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 5, 2024
    Assignee: SAVANT TECHNOLOIGES LLC
    Inventors: Zhe Wang, Li Jiang, Jing Chen, Hai Huang, Jie Gao, Kun Xiao, Jiachen Yang