Abstract: A decision feedback equalizer includes: a feedforward equalizer, a feedback equalizer, a slicer and a decision adjustment unit. The feedforward equalizer is arranged to generate a feedforward output signal based on an input signal. The feedback equalizer is coupled to the feedforward equalizer and arranged to generate a feedback output signal according to a decision output signal. The slicer is coupled to the feedforward equalizer and the feedback equalizer, and is controllable by a decision adjustment parameter, wherein the slicer is arranged to perform a slicer decision on a sum of the feedforward output signal and the feedback output signal, thereby generating the decision output signal. The decision adjustment unit is coupled to the slicer, and is arranged to adjust the decision adjustment parameter according to a sleep state of a communication device in which the decision feedback equalizer is disposed.

Abstract: A receiver includes an equalizer circuit, a radio frequency interference cancellation circuitry, and a channel estimation circuitry. The equalizer circuit is configured to process a first data signal according to a control signal, in order to generate a second data signal. The radio frequency interference cancellation circuitry is configured to detect a radio frequency interference signal according to the second data signal to generate radio frequency interference information, and to output a correction signal according to the radio frequency interference information, in order to correct the second data signal. The channel estimation circuitry configured to analyze a plurality of sets of signal components in the second data signal, and to utilize a power ratio of one of the plurality of sets of signal components to generate the control signal.

Abstract: A signal processing device includes a decision feedback equalizer and a coefficient adjusting circuit. The decision feedback equalizer includes a first equalizer configured to perform filtering on a first signal according to a set of first coefficients to generate a first filtered signal. The set of first coefficients includes multiple first coefficients. The coefficient adjusting circuit is configured to adaptively adjust one or more of the first coefficients according to an error signal. A limit operation of the first coefficients is selectively performed. When the limit operation of the first coefficients is performed, at least one of the first coefficients is set to a first predetermined value to generate a set of limited first coefficients.

Abstract: A transmission circuit includes a data input pin, a serial-to-parallel converter, an interface decoder, a parallel-to-serial converter, and a processor circuit. The serial-to-parallel converter is electrically coupled to the data input pin. The serial-to-parallel converter converts a plurality of data signals received by the first data input pin into a set of parallel data signals. The interface decoder is electrically coupled to the serial-to-parallel converter. The interface decoder decodes the set of parallel data signals to generate a set of decoded data signals for parallel transmission. The parallel-to-serial converter is electrically coupled to the interface decoder. The parallel-to-serial converter converts the set of decoded data signals into a plurality of input data signals for serial transmission. The processor circuit is electrically coupled to the parallel-to-serial converter. The processor circuit receives and processes the plurality of input data signals.

Abstract: A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.

Abstract: The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.

Abstract: Disclosed is an interference canceller capable of generating a cancellation signal for reducing cross port alien near-end (XPAN) crosstalk of a reception signal received by a receiver of a network device.

Abstract: A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.

Abstract: A signal processing method is provided. The signal processing method is used in a Gigabit Ethernet system including a device under test (DUT) and a link partner (LP), and includes the following steps. Firstly, an interference detector is configured to detect whether the Gigabit Ethernet system is interfered by other signal sources. Next, a physical layer (PHY) of the DUT or a PHY of the LP is used to, in response to the Gigabit Ethernet system being interfered by the other signal sources, set a request signal indicating whether or not the physical layer enters a low power idle (LPI) mode as FALSE. Which PHY of the DUT and the LP is used to set the request signal indicating whether or not the PHY enters the LPI mode as FALSE depends upon which one of the DUT and the LP is provided with the interference detector.

Abstract: A signal processing method in a digital-domain includes: adding a random number sequence signal into a time-domain input signal to generate a time-domain processed input signal; performing a Fourier transform operation upon the time-domain processed input signal to generate a frequency-domain processed input signal; performing an equalizer operation upon the frequency-domain processed input signal to generate a frequency-domain output signal according to coefficients of the equalizer operation; performing an inverse Fourier transform operation upon the frequency-domain output signal to generate a time-domain output signal; generating a decision output signal and generating a time-domain error signal according to the time-domain output signal; and determining the coefficients according to the time-domain error signal and the frequency-domain processed input signal.

Abstract: An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

Abstract: An echo cancelling system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a first transmitted signal. The first transmitted signal has a first sampling rate. The echo canceller circuit is configured to generate a second transmitted signal according to the first transmitted signal. The second transmitted signal has a second sampling rate. The second sampling rate is greater than the first sampling rate. The echo canceller circuit is further configured to generate an echo cancelling signal according to the second transmitted signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal.

Abstract: A receiving end of an electronic device includes an analog front end (AFE) circuit, a phase detector (PD), and a calculation circuit. The AFE circuit receives an input signal and adjusts the phase of the input signal according to a phase control signal. The PD detects the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculates a target phase value according to the phase difference accumulated value, and generates a first phase driving value according to the target phase value and the current phase value. The calculation circuit generates the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first and second phase driving values.

Abstract: A signal processing method in a digital-domain includes: adding a random number sequence signal into a time-domain input signal to generate a time-domain processed input signal; performing a Fourier transform operation upon the time-domain processed input signal to generate a frequency-domain processed input signal; performing an equalizer operation upon the frequency-domain processed input signal to generate a frequency-domain output signal according to coefficients of the equalizer operation; performing an inverse Fourier transform operation upon the frequency-domain output signal to generate a time-domain output signal; generating a decision output signal and generating a time-domain error signal according to the time-domain output signal; and determining the coefficients according to the time-domain error signal and the frequency-domain processed input signal.

Abstract: A signal processing circuit, which includes: a first clock source, configured to generate a first clock signal; a phase adjusting circuit, configured to receive the first clock signal, and to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; an error compensating circuit, configured to compensate an input signal according to an error signal, to generate an compensated input signal; an error calculating circuit, configured to generate the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiving end ADC (Analog to Digital Converter), configured to sample the compensated input signal according to the second clock signal.

Abstract: A signal processing circuit, which includes: a first clock source, configured to generate a first clock signal; a phase adjusting circuit, configured to receive the first clock signal, and to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; an error compensating circuit, configured to compensate an input signal according to an error signal, to generate an compensated input signal; an error calculating circuit, configured to generate the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiving end ADC (Analog to Digital Converter), configured to sample the compensated input signal according to the second clock signal.

Abstract: The present invention provides a transceiver. The transistor is coupled to a transmission line. The transceiver includes a variable resistor set, a transmitter module, a receiver module, and a digital signal processor. The transmitter module has an output terminal coupled to the variable resistor set and the transmission line. The transmitter module includes a first digital-to-analog converter configured to output an emission current. The receiver module has an input terminal coupled to the transmitter module and the transmission line. When the emission current is fed into the transmission line, a far-end echo is fed into the receiver module. An amplitude of the far-end echo is associated with a resistance value of the transmission line. The digital signal processor adjusts a current value of the emission current from a first default current value to a second default current value based on the amplitude of the far-end echo.

Abstract: A receiver includes an equalizer circuit, a radio frequency interference cancellation circuitry, and a channel estimation circuitry. The equalizer circuit is configured to process a first data signal according to a control signal, in order to generate a second data signal. The radio frequency interference cancellation circuitry is configured to detect a radio interference signal according to the second data signal to generate radio interference information, and to output a correction signal according to the radio interference information, in order to correct the second data signal. The channel estimation circuitry configured to analyze a plurality of sets of signal components in the second data signal, and to utilize a power ratio of one of the plurality of sets of signal components to generate the control signal.

Abstract: A receiver includes a first data slicer circuit and a radio interference detector circuitry. The first data slicer circuit is configured to generate a second data signal according to a first data signal. The radio interference detector circuitry is configured to generate first estimated information according to the first data signal, to generate second estimated information according to the second data signal, to generate third estimated information according to the first data signal and the second data signal, and to detect a radio interference signal according to the first estimated information, the second estimated information, and the third estimated information.

Abstract: A receiver includes a first data slicer circuit and a radio interference detector circuitry. The first data slicer circuit is configured to generate a second data signal according to a first data signal. The radio interference detector circuitry is configured to generate first estimated information according to the first data signal, to generate second estimated information according to the second data signal, to generate third estimated information according to the first data signal and the second data signal, and to detect a radio interference signal according to the first estimated information, the second estimated information, and the third estimated information.