Patents by Inventor Lih-Ping Li
Lih-Ping Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7897505Abstract: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.Type: GrantFiled: March 23, 2007Date of Patent: March 1, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Chi Ko, Lih-Ping Li, Yung-Cheng Lu, Hui-Lin Chang, Chih-Hsien Lin
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Patent number: 7456093Abstract: A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.Type: GrantFiled: July 3, 2004Date of Patent: November 25, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Tsung Chen, Keng-Chu Lin, Hui-Lin Chang, Lih-Ping Li, Tien-I Bao, Yung-Cheng Lu, Syun-Ming Jang
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Publication number: 20080233765Abstract: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Inventors: Chung-Chi Ko, Lih-Ping Li, Yung-Cheng Lu, Hui-Lin Chang, Chih-Hsien Lin
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Patent number: 7320945Abstract: A thin film dielectric layer comprises a top portion and a bottom portion and has density and permittivity characteristics that vary substantially uniformly from the top portion to the bottom portion. Control over the density and/or permittivity is accomplished through varying deposition parameters such as flow rate of constituent process gases or deposition chamber pressure, or through a post deposition treatment, such as plasma treatment or curing.Type: GrantFiled: June 30, 2004Date of Patent: January 22, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lih-Ping Li, Syun-Ming Jang
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Publication number: 20070264843Abstract: A method for manufacturing an integrated circuit is provided. In one example, the method includes forming a substantially nitrogen-free silicon carbide layer over a substrate using a methyl silicate gas.Type: ApplicationFiled: May 9, 2006Publication date: November 15, 2007Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lih-Ping Li, Yung-Cheng Lu, Tien-I. Bao, Syun-Ming Jang, Ying-Tsung Chen
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Patent number: 7288284Abstract: A method for seasoning a process chamber is disclosed. The seasoning method includes providing a seasoning film on the interior surfaces of a process chamber, typically after cleaning of the chamber.Type: GrantFiled: March 26, 2004Date of Patent: October 30, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lih-Ping Li, Yung-Chen Lu
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Publication number: 20060205232Abstract: A method for etching a dielectric material in a semiconductor device is disclosed. After providing a conductive region, a dielectric layer is formed over the conductive region. A dielectric antireflective coating (DARC) layer is further formed on the dielectric layer. Then, a moisture-removal step is performed that removes moisture from the DARC layer and from an interface region between the dielectric and the DARC layer. A masking pattern is transferred into the DARC layer and the dielectric layer.Type: ApplicationFiled: March 10, 2005Publication date: September 14, 2006Inventors: Lih-Ping Li, Tzong-Sheng Chang, William Kuo, Tsung-Hsien Lee, Chun-Lin Tsai, Szu-An Wu, Yin-Ping Lee
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Publication number: 20060115980Abstract: A method of forming a low dielectric constant film that can be used in a damascene process is disclosed. An organosilicon precursor such as octamethylcyclotrisiloxane (OMCTS) or any other compound that contains Si, C, and H and optionally O is transported into a PECVD chamber with a carrier gas such as CO or CO2 to provide a soft oxidation environment that leads to a higher carbon content and low k value in the deposited film. The carrier gas may replace helium or argon that have a higher bombardment property that can damage the substrate. Since CO and CO2 can contribute carbon to the deposited film, a lower k value is achieved than when an inert carrier gas is employed. The deposited film can be employed, for example, as a dielectric layer in a damascene stack or as an etch stop layer.Type: ApplicationFiled: May 16, 2005Publication date: June 1, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chi Ko, Lih-Ping Li, Lain-Jong Li, Syun-Ming Jang
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Patent number: 7001833Abstract: A method for etching contact/via openings in low-k dielectric layers is described. The method introduces a carbon deficient ARL which is compatible with the acidic photoresists used by DUV photolithography. The carbon deficiency of the ARL permits the use of fluorocarbon plasma etching ambients to etch the openings in the low-k layers without excessive polymer formation, thereby eliminating polymer pinch-off during the etching of deep, high aspect ratio contacts and vias in sub-tenth micron integrated circuit technology. Vertical walled contact and via openings may be formed using a DUV photoresist mask and non-oxygen containing fluorocarbon etching plasmas. An additional hardmask is therefore not needed. For non-carbon containing low-k dielectric layers the openings may be etched in simple fluorocarbon plasmas without excessive polymer formation.Type: GrantFiled: March 25, 2004Date of Patent: February 21, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-J Bao, Lih-Ping Li, Syun-Ming Jang
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Publication number: 20060003598Abstract: A thin film dielectric layer comprises a top portion and a bottom portion and has density and permittivity characteristics that vary substantially uniformly from the top portion to the bottom portion. Control over the density and/or permittivity is accomplished through varying deposition parameters such as flow rate of constituent process gases or deposition chamber pressure, or through a post deposition treatment, such as plasma treatment or curing.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Inventors: Lih-Ping Li, Syun-Ming Jang
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Publication number: 20060003572Abstract: A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.Type: ApplicationFiled: July 3, 2004Publication date: January 5, 2006Inventors: Pi-Tsung Chen, Keng-Chu Lin, Hui-Lin Chang, Lih-Ping Li, Tien-I Bao, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 6962869Abstract: A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.Type: GrantFiled: October 15, 2002Date of Patent: November 8, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-I Bao, Hsin-Hsien Lu, Lih-Ping Li, Chung-Chi Ko, Aaron Song, Syun-Ming Jang
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Patent number: 6958524Abstract: A method of manufacturing an insulating layer, including forming a first dielectric layer having a first pore size over a substrate, shrinking the first pore size to a second pore size by a first densification process, forming a second dielectric layer over the first dielectric layer, and increasing an aggregate dielectric constant of the first and second dielectric layers by a second densification process.Type: GrantFiled: November 6, 2003Date of Patent: October 25, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lih-Ping Li, Yung-Cheng Lu
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Publication number: 20050214455Abstract: A method for seasoning a process chamber is disclosed. The seasoning method includes providing a seasoning film on the interior surfaces of a process chamber, typically after cleaning of the chamber.Type: ApplicationFiled: March 26, 2004Publication date: September 29, 2005Inventors: Lih-Ping Li, Yung-Chen Lu
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Patent number: 6924242Abstract: A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.Type: GrantFiled: October 23, 2003Date of Patent: August 2, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Syun-Ming Jang, Chung-Chi Ko, Tien-I Bao, Lih-Ping Li, Al-Sen Liu
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Publication number: 20050140029Abstract: The present invention provides for a heterogeneous low k dielectric comprising a main layer and a sub-layer. The main layer comprises a first low k dielectric material with a first low k dielectric constant and the sub-layer comprises a second low k dielectric material with a second low k dielectric constant. The sub-layer directly adjoins the main layer, and the second low k dielectric constant is greater than the first low k dielectric constant by more than 0.1.Type: ApplicationFiled: October 28, 2004Publication date: June 30, 2005Inventors: Lih-Ping Li, Syun-Ming Jang, Pi-Tsung Chen, Yung-Cheng Lu
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Publication number: 20050133931Abstract: A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.Type: ApplicationFiled: February 1, 2005Publication date: June 23, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Syun-Ming Jang, Chung-Chi Ko, Tien-I Bao, Lih-Ping Li, Ai-Sen Liu
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Publication number: 20050130411Abstract: A method for etching contact/via openings in low-k dielectric layers is described. The method introduces a carbon deficient ARL which is compatible with the acidic photoresists used by DUV photolithography. The carbon deficiency of the ARL permits the use of fluorocarbon plasma etching ambients to etch the openings in the low-k layers without excessive polymer formation, thereby eliminating polymer pinch-off during the etching of deep, high aspect ratio contacts and vias in sub-tenth micron integrated circuit technology. Vertical walled contact and via openings may be formed using a DUV photoresist mask and non-oxygen containing fluorocarbon etching plasmas. An additional hardmask is therefore not needed. For non-carbon containing low-k dielectric layers the openings may be etched in simple fluorocarbon plasmas without excessive polymer formation.Type: ApplicationFiled: March 25, 2004Publication date: June 16, 2005Inventors: Tien-J Bao, Lih-Ping Li, Syun-Ming Jang
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Publication number: 20050101119Abstract: A method of manufacturing an insulating layer, including forming a first dielectric layer having a first pore size over a substrate, shrinking the first pore size to a second pore size by a first densification process, forming a second dielectric layer over the first dielectric layer, and increasing an aggregate dielectric constant of the first and second dielectric layers by a second densification process.Type: ApplicationFiled: November 6, 2003Publication date: May 12, 2005Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lih-Ping Li, Yung-Cheng Lu
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Publication number: 20050090122Abstract: A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.Type: ApplicationFiled: October 23, 2003Publication date: April 28, 2005Inventors: Syun-Ming Jang, Chung-Chi Ko, Tien-I Bao, Lih-Ping Li, Ai-Sen Liu