Patents by Inventor Lih-Ping Li
Lih-Ping Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6884659Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.Type: GrantFiled: August 15, 2003Date of Patent: April 26, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Trong Chen, Lain-Jong Li, Syun-Ming Jang, Shu E Ku, Tien I. Bao, Lih-Ping Li
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Patent number: 6867126Abstract: A method of increasing the cracking threshold of a low-k material layer comprising the following steps. A substrate having a low-k material layer formed thereover is provided. The low-k material layer having a cracking threshold. The low-k material layer is plasma treated to increase the low-k material layer cracking threshold. The plasma treatment including a gas that is CO2, He, NH3 or combinations thereof.Type: GrantFiled: November 7, 2002Date of Patent: March 15, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lih-Ping Li, Yung-Chen Lu, Chung-Chi Ko
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Publication number: 20040266216Abstract: A method for forming a low k dielectric material block is provided. In one example, the method includes depositing a low k dielectric layer over a semiconductor substrate and curing the deposited low k dielectric layer. The curing may be performed using a remote plasma process in which an excitation gas is excited in a selected region remote from the deposited low k dieletric layer to carry radiation energy and transfer to the low k dielectric layer when the excitation gas contacts the low k dielectric layer.Type: ApplicationFiled: April 20, 2004Publication date: December 30, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lih-Ping Li, Yung-Chen Lu, Syun-Ming Jang
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Publication number: 20040219795Abstract: A new method is provided for the improvement of breakdown performance of a layer of dielectric and the removal of a layer of copper oxide (CuO) from copper interconnects. The formed layer of dielectric, thereby including a formed layer of CuO or Cu2O is, using the invention, exposed to a H2 plasma treatment. The H2 plasma treatment reduces the dielectric constant of the exposed and surrounding layer of low-k dielectric while at the same time removing the layer of CuO.Type: ApplicationFiled: May 1, 2003Publication date: November 4, 2004Applicant: Taiwan Semiconductor Manufacturing Co.Inventors: Lih-Ping Li, Tien-I Bao, Syun-Ming Jang
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Patent number: 6812043Abstract: A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.Type: GrantFiled: April 25, 2002Date of Patent: November 2, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-I Bao, Chung-Chi Ko, Lih-Ping Li, Syun-Ming Jang
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Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer
Patent number: 6770570Abstract: A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.Type: GrantFiled: November 15, 2002Date of Patent: August 3, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lih-Ping Li, Hsin-Hsien Lu, Syun-Ming Jang -
Patent number: 6756321Abstract: A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process. The capping layer of the present invention has improved adhesion and a reduced dielectric constant with comparable current leakage compared to capping layers of the prior art.Type: GrantFiled: October 5, 2002Date of Patent: June 29, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chung-Chi Ko, Yung-Cheng Lu, Lain-Jong Li, Lih-Ping Li, Yu-Huei Chen, Shu-E Ku
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Patent number: 6753269Abstract: The present disclosure provides a method for forming an intermediate trench layer through low k dielectric material deposition in a damascene process for manufacturing semiconductor devices. After depositing a low k dielectric material block, a curing process is applied to the low k dielectric material block for a predetermined curing time period, wherein after the curing time period, the low k dielectric material block forms a first and second low k dielectric layers so as to make the first low k dielectric layer an intermediate trench layer, thereby eliminating the need of an etch stop layer.Type: GrantFiled: May 8, 2003Date of Patent: June 22, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lih-Ping Li, Yung-Chen Lu, Syun-Ming Jang
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Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer
Publication number: 20040097099Abstract: A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.Type: ApplicationFiled: November 15, 2002Publication date: May 20, 2004Inventors: Lih-Ping Li, Hsin-Hsien Lu, Syun-Ming Jang -
Publication number: 20040067658Abstract: A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process.Type: ApplicationFiled: October 5, 2002Publication date: April 8, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Chi Ko, Yung-Cheng Lu, Lain-Jong Li, Lih-Ping Li, Yu-Huei Chen, Shu-E Ku
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Publication number: 20040063308Abstract: A method for etching contact/via openings in low-k dielectric layers is described The method introduces a carbon deficient ARL which is compatible with the acidic photoresists used by DUV photolithography. The carbon deficiency of the ARL permits the use of fluorocarbon plasma etching ambients to etch the openings in the low-k layers without excessive polymer formation, thereby eliminating polymer pinch-off during the etching of deep, high aspect ratio contacts and vias in sub-tenth micron integrated circuit technology. Vertical walled contact and via openings may be formed using a DUV photoresist mask and non-oxygen containing fluorocarbon etching plasmas. An additional hardmask is therefore not needed. For non-carbon containing low-k dielectric layers the openings may be etched in simple fluorocarbon plasmas without excessive polymer formation.Type: ApplicationFiled: September 27, 2002Publication date: April 1, 2004Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Tien-I Bao, Lih-Ping Li, Syun-Ming Jang
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Publication number: 20040038550Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.Type: ApplicationFiled: August 15, 2003Publication date: February 26, 2004Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Bi-Trong Chen, Lain-Jong Li, Syun-Ming Jang, Shu E. Ku, Tien I. Bao, Lih-Ping Li
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Publication number: 20030203652Abstract: A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an organo-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.Type: ApplicationFiled: April 25, 2002Publication date: October 30, 2003Inventors: Tien-I Bao, Chung-Chi Ko, Lih-Ping Li, Syun-Ming Jang
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Patent number: 6623654Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.Type: GrantFiled: November 9, 2001Date of Patent: September 23, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Bi-Trong Chen, Lain-Jong Li, Syun-Ming Jang, Shu E Ku, Tien I. Bao, Lih-Ping Li
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Patent number: 6602780Abstract: A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.Type: GrantFiled: September 6, 2001Date of Patent: August 5, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tsu Shih, Yung-Cheng Lu, Lih Ping Li, Tien-I Bao, Chung Chi Ko
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Publication number: 20030089678Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.Type: ApplicationFiled: November 9, 2001Publication date: May 15, 2003Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Bi-Trong Chen, Lain-Jong Li, Syun-Ming Jang, Shu E. Ku, Tien I. Bao, Lih-Ping Li
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Publication number: 20030045124Abstract: A method is presented for forming a protective oxide liner including providing an insulating layer over a conductive layer; providing an anti-reflectance layer over the insulating layer; providing an etching stop layer over the anti-reflectance layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the insulating layer; depositing an oxide liner such that the sidewalls of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from said surface.Type: ApplicationFiled: September 6, 2001Publication date: March 6, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsu Shih, Yung-Cheng Lu, Lih Ping Li, Tien-I Bao, Chung Chi Ko
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Patent number: 6426371Abstract: The invention provides a fast-cured sol material, which is produced by hydrolysis and condensation of the following starting materials: 2-60 parts by weight of a silicon alkoxide; 20-98 parts by weight of an alcohol; 0.5-50 parts by weight of an aqueous media; 0.0001-10 parts by weight of a base; 0.001-30 parts by weight of at least one additive; and optionally 0.0001-10 parts by weight of an acid. A coating of the sol material according to the invention can be directly cured (without aging) to obtain a microporous dielectric film without shrinkage or cracks.Type: GrantFiled: July 1, 1999Date of Patent: July 30, 2002Assignees: Industrial Technology Research Institute, Chinese Petroleum Corporation, Taiwan Fertilizer Co., Ltd.Inventors: Lih-Ping Li, Li-Mei Chen, Chao-Jen Wang, Hsin-Hsen Lu