Abstract: A signal generating circuit and a signal generating method, a driving circuit of a light emitting device and a display device. The signal generating circuit includes: a control circuit, configured to calculate at least one of frequency control word information or duty-cycle control word information according to an instruction; and a pulse-width adjusting circuit, configured to generate a pulse signal according to the at least one of the frequency control word information or the duty-cycle control word information.

Abstract: The present disclosure relates to a frequency source with an adjustable frequency, and related system, method and electronic device, in particular to a frequency source with an adjustable frequency comprising an input terminal for receiving an input voltage signal, wherein the frequency source identifies a frequency of the input voltage signal. The present disclosure relates to a system comprising the frequency source, a method for identifying the frequency of the voltage signal, and an electronic device comprising the frequency source.

Abstract: An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.

Abstract: The present disclosure relates to a frequency source with an adjustable frequency, and related system, method and electronic device, in particular to a frequency source with an adjustable frequency comprising an input terminal for receiving an input voltage signal, wherein the frequency source identifies a frequency of the input voltage signal. The present disclosure relates to a system comprising the frequency source, a method for identifying the frequency of the voltage signal, and an electronic device comprising the frequency source.

Abstract: A frequency compensator, an electronic device, and a frequency compensation method are disclosed. The frequency compensator includes a control circuit and a frequency compensation circuit. The control circuit is configured to generate a frequency control word according to an initial frequency and an target frequency. The frequency compensation circuit is configured to receive an input signal of an initial frequency, and to generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency.

Abstract: A signal generating circuit and a signal generating method, a driving circuit of a light emitting device and a display device. The signal generating circuit includes: a control circuit, configured to calculate at least one of frequency control word information (or duty-cycle control word information according to an instruction; and a pulse-width adjusting circuit, configured to generate a pulse signal according to the at least one of the frequency control word information or the duty-cycle control word information.

Abstract: An electronic device includes: an acquisition circuit, configured to collect the current environmental information for characterizing the environment of the electronic device; a processing circuit, configured to receive the current environmental information from the acquisition circuit; determine a target frequency control word corresponding to the current environmental information according to a preset expected operating status of the electronic device; and input the target frequency control word to the TAF-DPS clock generator; the TAF-DPS clock generator, configured to generate a clock signal according to the target frequency control word, and output the clock signal to a functional circuit; the functional circuit, configured to operate in accordance with the clock signal to make the electronic device reach the expected operating status.

Abstract: The present application provides a signal generator, comprising a control circuit configured to receive input information, and generate variable control word information based on the received input information; a base time unit generation circuit configured to generate a base time unit; and a signal generation circuit configured to receive the variable control word information from the control circuit and receive the base time unit from the base time unit generation circuit, and generate a target signal having a variable frequency based on the received variable control word information and the received base time unit.

Abstract: A digitally controlled oscillator, including: a frequency divider chain, configured to perform frequency division on an input clock signal to produce K basic clock signals, wherein frequencies and periods of the K basic dock signals are the same and a time difference between two adjacent basic clock signals is a basic time unit: and a frequency synthesizer, configured to receive the K basic clock signals from the frequency divider chain, determine a first period and a second period according to the basic time unit and a frequency control word, and generate a synthetic clock signal based on the K basic clock signals, wherein the synthetic clock signal uses the first period and the second period in an alternate manner.

Abstract: A frequency compensator, an electronic device, and a frequency compensation method are disclosed. The frequency compensator includes a control circuit and a frequency compensation circuit. The control circuit is configured to generate a frequency control word according to an initial frequency and an target frequency. The frequency compensation circuit is configured to receive an input signal of an initial frequency, and to generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency.

Abstract: The present application provides a signal generator, comprising a control circuit configured to receive input information, and generate variable control word information based on the received input information; a base time unit generation circuit configured to generate a base time unit; and a signal generation circuit configured to receive the variable control word information from the control circuit and receive the base time unit from the base time unit generation circuit, and generate a target signal having a variable frequency based on the received variable control word information and the received base time unit.

Abstract: An interface adapter for facilitating the data communication among computation modules in a Network-on-Chip SoC comprises 1) a FIFO block having certain number of storage cells for temporarily storing the data to be transported between two communicating modules; 2) a TAF-DPS clock generator and a multi-phase generator attached at the FIFO write side for generating the write clock for FIFO and the driving clock for the transmitter, a TAF-DPS clock generator and a multi-phase generator attached at the FIFO read side for generating the read clock for FIFO and the driving clock for the receiver; 3) a write pointer controller and a read pointer controller for reading the FIFO status and controlling the TAF-DPS clock generators at the write side and at the read side, respectively. A design scheme of using said interface adapters in Network-on-Chip SoC design includes a plurality of computation modules, routing modules, said interface adapters, a network of communication link, a network of global clock distribution.

Abstract: Circuits of a TAF-DPS clock generator implemented on programmable logic chip comprise: 1) a base time unit generator created from configurable blocks, or on-chip PLL, or on-chip DLL, said base time unit generator produces a plurality of phase-evenly-spaced-signals; 2) a TAF-DPS frequency synthesizer created by configuring configurable blocks of said programmable logic chip, said TAF-DPS frequency synthesizer takes said plurality of phase-evenly-spaced-signals as its input.

Abstract: Circuits for distributing a global clock signal to all clock sinks on a chip for synchronous operation comprises 1) a plurality of synchronous clock areas (SCA), each SCA having a Time-Average-Frequency Direct Period Synthesis (TAF-DPS) clock source for generating a function clock, said TAF-DPS clock source has frequency synthesis and phase adjustment capabilities on its output of function clock; 2) a network for distributing a low frequency global clock signal to said plurality of synchronous clock areas, said global clock signal is used as reference for said TAF-DPS clock sources in all SCAs; 3) a plurality of clock sinks in each SCA, said clock sinks are driven by said function clock generated from said TAF-DPS clock source. Methods of distributing a low frequency global clock signal to all clock sinks in a chip for synchronous operation are also disclosed.

Abstract: Circuits for measuring TOF between two electrical signals comprises 1) a slow TAF-DPS clock signal generator for generating a slow clock signal, a fast TAF-DPS clock signal generator for generating a fast clock signal, said slow TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer, said fast TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer; 2) a phase detector for receiving said slow and fast clock signals and detecting point-of-coincidence between said slow and fast clock signals; 3) a first digital counter driven by said slow clock signal for storing the number of slow clock cycles and a second digital counter driven by said fast clock signal for storing the number of fast clock cycles; 4) a calibrator for calibrating said gate ring oscillators; 5) a calculation block for calculating TOF measurement result.

Abstract: A microelectronic system comprises at least one circuit block that performs certain signal processing functions and at least one clock generation circuit that produces at least one Time-Average-Frequency clock signal which comprises clock pulses of at least two different lengths. The said lengths are measured in time. The arithmetic mean of the lengths of all the pulses that exist in a time frame of one second is calculated. The Time-Average-Frequency clock pulse train is made in such way that the arithmetic inversion of the said arithmetic mean equals to a predetermined value that is the clock frequency of the Time-Average-Frequency clock signal. At least one said circuit block in the said microelectronic system is driven by the said Time-Average-Frequency clock signal. The said circuit block is setup-constrained using the minimum pulse length found among the lengths of all the pulses in the Time-Average-Frequency clock signal.

Abstract: One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

Abstract: An adaptive clock generation circuit for synthesizing Time-Average-Frequency in dynamic fashion includes (a) a timing circuit for generating a base unit of fixed time span, (b) a control circuit that takes inputs from a microelectronic system wherein the control circuit and the clock generation circuit reside, for generating a update signal and a frequency control word, (c) a direct period synthesizer for generating a plurality of types of pulses by utilizing said base unit and the frequency control word, for creating a segment of a clock pulse train by connecting electrical pulses in series that are selected from said plurality of types according to the update signal, for creating the entire clock pulse train by connecting said segment in series. The resulting Time-Average-Frequency of the clock pulse train matches a selected frequency that is required by the operation of the microelectronic system wherein the clock generation circuit resides.

Abstract: A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state.

Abstract: An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.