Patents by Inventor Lin Lee

Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984489
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
  • Patent number: 11984410
    Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
  • Patent number: 11983370
    Abstract: A two dimensional touch sensor panel can be thermoformed or curved by another process to a three-dimensional touch sensor panel, and the three-dimensional touch sensor panel can be laminated to a three-dimension surface having a highly curved or spherical shape. In some examples, thermoforming a two-dimensional touch sensor panel into a three-dimensional touch sensor panel can result in strain of the touch electrodes, and can result in non-uniform three-dimensional touch electrodes (distortion of the two-dimensional touch electrode pattern). The strain can be a function of the curved touch-sensitive surface and/or process related mechanical strain from thermoforming. In some examples, a three-dimensional touch sensor panel can be formed with uniform area touch electrodes using a two-dimensional touch sensor panel pattern with non-uniform area touch electrodes in accordance with the strain pattern expected for a given curved surface and thermoforming technique.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 14, 2024
    Assignee: Apple Inc.
    Inventors: Supratik Datta, Karan Jain, Zhiyuan Sun, Ho Hyung Lee, Da Yu, Wei Lin, Nathan K. Gupta, Chun-Chih Chang
  • Publication number: 20240155758
    Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
  • Publication number: 20240153870
    Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240153950
    Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
  • Publication number: 20240145719
    Abstract: A binder solution for an all-solid-state battery, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same, and more particularly to a binder solution for an all-solid-state battery, in which a polymer binder configured such that a non-polar functional group is bonded to the end of a polar functional group is used, whereby the polar functional group is provided by a deprotection mechanism of the polymer binder through a thermal treatment, thus increasing adhesion between electrode materials to thereby improve battery capacity and enabling a wet process to thereby reduce manufacturing costs, an electrode slurry for an all-solid-state battery including the same and a method of manufacturing an all-solid-state battery using the same.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation, Seoul National University R&DB Foundation
    Inventors: Sang Mo Kim, Sang Heon Lee, Yong Sub Yoon, Jae Min Lim, Ju Yeong Seong, Jin Soo Kim, Jang Wook Choi, Kyu Lin Lee, Ji Eun Lee
  • Publication number: 20240145260
    Abstract: An airflow heating module for an equipment front-end module, including: a first perforated plate including a first plurality of holes used as airflow inlets; a second perforated plate including a second plurality of holes used as airflow outlets; a plurality of heaters provided between the first and the second perforated plates; and an active air intake device provided on the first perforated plate to accelerate airflow flowing through the first plurality of holes and past the plurality of heaters, such that the airflow carries heat generated by the heaters and passes through the second plurality of holes. Each of the heaters includes a heating tube and a fin. The fin is formed helically around the heating tube and attached thereto.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Inventors: Yueh-Lin CHIANG, Hsin-Jan PAI, Ying-Feng LEE, Ling-Chiao HUANG
  • Publication number: 20240139301
    Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 2, 2024
    Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240140200
    Abstract: A displaying method and a displaying system for a vehicle, include obtaining a current date; determining whether to set an image of a holiday or anniversary to be displayed on a display of the vehicle by providing a display setting option to select or not to select a display setting option of a user; providing a display setting option and receiving a user's selection of the display setting option; when the display setting option is selected, comparing the obtained current date with preset holiday data and/or the preset anniversary data to determine whether the current date is a holiday corresponding to the preset holiday data, or determine whether the current date is an anniversary corresponding to the preset anniversary data; and displaying a pre-stored image related to the holiday and/or anniversary of the current date on a display of the vehicle.
    Type: Application
    Filed: May 15, 2023
    Publication date: May 2, 2024
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Xiao Jia YAN, Jin Young LEE, Da Lin Zheng
  • Publication number: 20240144863
    Abstract: An electronic device able to be operated with a first state and a second state includes a substrate and electronic units. In a top view, the substrate has a first area in the first state and a second area in the second state, and the second area is greater than the first area. The electronic units are disposed on the substrate. The number of the electronic units being in a mode of ON in the second state is greater than that in the first state. The electronic device has a PPA_1 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the first state, and a PPA_2 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the second state, 1.5×PPA_1?PPA_2?0.5×PPA_1.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: InnoLux Corporation
    Inventors: Yuan-Lin Wu, Chan-Feng Chiu, Kuan-Feng Lee
  • Publication number: 20240145381
    Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Patent number: 11972975
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
  • Patent number: 11973261
    Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a metallic housing, a first feed portion, and a second feed portion. The metallic housing includes a metallic side frame and a metallic back board. The metallic side frame defines a slot, and first and second gaps. The metallic side frame between the first gap and one end of the slot forms a first radiation portion. The second gap divides the first radiation portion into first and second radiation sections. The first feed portion feeds current and signal to the first radiation section, and the first radiation section works in a GPS mode and a WIFI 2.4 GHz mode. The second feed portion feeds current and signal to the second radiation section, and the second radiation section works in a WIFI 5 GHz mode.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Kun-Lin Sung, Yung-Chin Chen, Yi-Chieh Lee
  • Patent number: 11971519
    Abstract: A display article is described herein that includes: a substrate comprising a thickness and a primary surface; a textured surface region; and an antireflective coating disposed on the textured surface region. The textured surface region comprises structural features and an average texture height (Rtext) from 50 nm to 300 nm. The substrate exhibits a sparkle of less than 5%, as measured by PPD140, and a transmittance haze of less than 40%, at a 0° incident angle. The antireflective coating comprises alternating high refractive index and low refractive index layers. Each of the low index layers comprises a refractive index of less than or equal to 1.8, and each of the high index layers comprises a refractive index of greater than 1.8. The article also exhibits a first-surface average photopic specular reflectance (% R) of less than 0.3% at any incident angle from about 5° to 20° from normal at visible wavelengths.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 30, 2024
    Assignee: CORNING INCORPORATED
    Inventors: Shandon Dee Hart, Karl William Koch, III, Carlo Anthony Kosik Williams, Lin Lin, Cameron Robert Nelson, James Joseph Price, Jayantha Senawiratne, Florence Christine Monique Verrier, David Lee Weidman
  • Patent number: 11973772
    Abstract: Conventional email filtering services are not suitable for recognizing sophisticated malicious emails, and therefore may allow sophisticated malicious emails to reach inboxes by mistake. Introduced here are threat detection platforms designed to take an integrative approach to detecting security threats. For example, after receiving input indicative of an approval from an individual to access past email received by employees of an enterprise, a threat detection platform can download past emails to build a machine learning (ML) model that understands the norms of communication with internal contacts (e.g., other employees) and/or external contacts (e.g., vendors). By applying the ML model to incoming email, the threat detection platform can identify security threats in real time in a targeted manner.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 30, 2024
    Assignee: Abnormal Security Corporation
    Inventors: Sanjay Jeyakumar, Jeshua Alexis Bratman, Dmitry Chechik, Abhijit Bagri, Evan Reiser, Sanny Xiao Lang Liao, Yu Zhou Lee, Carlos Daniel Gasperi, Kevin Lau, Kai Jiang, Su Li Debbie Tan, Jeremy Kao, Cheng-Lin Yeh
  • Publication number: 20240133949
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Publication number: 20240136221
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee