Patents by Inventor Linda J. Rankin
Linda J. Rankin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7774600Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: December 27, 2007Date of Patent: August 10, 2010Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 7770005Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: December 27, 2007Date of Patent: August 3, 2010Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 7757081Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: December 27, 2007Date of Patent: July 13, 2010Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 7725713Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trust agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: December 27, 2007Date of Patent: May 25, 2010Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 7698552Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: GrantFiled: June 3, 2004Date of Patent: April 13, 2010Assignee: Intel CorporationInventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 7673090Abstract: Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.Type: GrantFiled: December 19, 2001Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Shivnandan D. Kaushik, Ling Cen, James B. Crossland, Mohan J. Kumar, Linda J. Rankin, David J. O'Shea
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Publication number: 20090319717Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: August 28, 2009Publication date: December 24, 2009Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 7617363Abstract: In one embodiment, a method is provided. The method of this embodiment provides detecting by a network controller a flush occurring on a host bus of a DM (“direct messaging”) packet to a memory from a first cache line associated with a first processor; obtaining and storing the DM packet at a second cache line associated with the network controller; and sending the DM packet over a network to a third cache line associated with a second processor.Type: GrantFiled: September 26, 2005Date of Patent: November 10, 2009Assignee: Intel CorporationInventors: Nagabhushan Chitlur, Linda J. Rankin, David S. Dunning, Maruti Gupta, Hongbin (Michael) Liao
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Patent number: 7603508Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: January 14, 2008Date of Patent: October 13, 2009Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20090106471Abstract: An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.Type: ApplicationFiled: November 14, 2008Publication date: April 23, 2009Inventors: Shivnandan D. Kaushik, James B. Crossland, Mohan J. Kumar, Linda J. Rankin, David J. O'Shea
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Patent number: 7493438Abstract: An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.Type: GrantFiled: October 3, 2001Date of Patent: February 17, 2009Assignee: Intel CorporationInventors: Shivnandan D. Kaushik, James B. Crossland, Mohan J. Kumar, Linda J. Rankin, David J. O'Shea
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Patent number: 7486685Abstract: A system for carrying two channels of data over a single physical connection. In multi-node systems, data packets are divided into flits with flits from two channels being interleaved and carried by a single physical connection. Once the flits are transmitted, they are reassembled into packets in order to be carried by a processor bus. Controllers for the channel communicate to minimize “bubbles” observed during packet assembly by the processor bus. Thus, the data is transferred in two different types of resource sharing paradigms.Type: GrantFiled: June 29, 2001Date of Patent: February 3, 2009Inventors: Linda J. Rankin, Suresh Chittor
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Publication number: 20080244222Abstract: The present disclosure provides a method for virtual processing. According to one exemplary embodiment, the method may include partitioning a plurality of cores of an integrated circuit (IC) into a plurality of virtual processors, the plurality of virtual processors having a framework dependent upon a programming application. The method may further include performing at least one task using the plurality of cores. Of course, additional embodiments, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: INTEL CORPORATIONInventors: Alexander V. Supalov, Hans-Christian Hoppe, Linda J. Rankin
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Publication number: 20080155256Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.Type: ApplicationFiled: December 27, 2007Publication date: June 26, 2008Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
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Patent number: 7346825Abstract: Error detection methods, systems and medium are provided. The error detection method may comprise processing error conditions associated with transactions in a manner that may enable error source identification. The system may comprise a plurality of nodes of components. The nodes may include storage elements to record an error condition indicative of whether a component provided an indication of detecting an error in response to processing the transaction.Type: GrantFiled: September 6, 2001Date of Patent: March 18, 2008Assignee: Intel CorporationInventors: Linda J. Rankin, David J. O'Shea
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Patent number: 7343442Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: June 6, 2006Date of Patent: March 11, 2008Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20080052463Abstract: A cache-coherent network interface includes registers or buffers addressable by a processor with reference to an address space of the processor. The processor and the cache-coherent network interface both share a common system bus. The registers or buffers are further cacheable into a cache of the processor with reference to the address space.Type: ApplicationFiled: August 25, 2006Publication date: February 28, 2008Inventors: Nagabhushan Chitlur, Linda J. Rankin, Paul M. Stillwell, Dennis R. Bradford
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Patent number: 7158911Abstract: An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.Type: GrantFiled: April 9, 2004Date of Patent: January 2, 2007Assignee: Intel CorporationInventors: Stephen H. Gunther, Frank Binns, Jack D. Pippin, Linda J. Rankin, Edward A. Burton, Douglas M. Carmean, John M. Bauer
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Patent number: 7117311Abstract: A computing device maintains coherency while supporting addition and removal of memory caching agents without rebooting the computing device.Type: GrantFiled: December 19, 2001Date of Patent: October 3, 2006Assignee: Intel CorporationInventors: Linda J. Rankin, Shivnandan D. Kaushik, James B. Crossland, Mohan J. Kumar, David J. O'Shea
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Patent number: 7058750Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: May 10, 2000Date of Patent: June 6, 2006Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar