Abstract: One aspect of the invention relates to a method for supporting hibernation despite the presence of hot-plugged nodes and non-deterministic boot operations. The method comprises invoking a management interrupt in response to a Hibernate request. The management interrupt is used to obtain and store platform configuration information into a non-volatile storage location. The platform configuration information includes data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence as well as a boot node identifier and a listing of an order in which processors of the platform are initialized.

Abstract: An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

Abstract: One aspect of the invention relates to creation of a container object being part of software that is stored in platform readable medium and executed by a processor within a platform. The container comprises (i) a hardware identification object to identify to an operating system of the platform that a type of device represented by the container object is a node and (ii) a plurality of component objects to identify constituent components of the node. Another aspect of the invention is the distribution of BIOS to handle initiation of components of a substrate in response to hot-plug addition of that substrate.

Abstract: A multi-port switch is incorporated into a multi-node computer system and at least a first port of the multi-port switch is assigned to a first domain.

Abstract: A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches is provided with a Pseudo Least-Recently-Used (PLRU) replacement algorithm to identify a least-recently-used (PLRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in the processor caches.

Abstract: An interrupt method, system, and/or medium may comprise generating a load balancing value that helps balance servicing of interrupts among processors.

Abstract: An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

Abstract: An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

Abstract: An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

Abstract: A method and system to prefetch data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected to a high speed bus, a CPU and a bus interface unit that allows the CPU to communicate with the high speed bus. The bus interface unit contains logic circuitry, so that when the CPU generates a read memory access request for information associated with a first address, the interface unit generates a request packet for the information and prefetch information associated with a prefetch address. The bus interface unit creates the request packet by increasing the number of addresses originally requested by the CPU. The interface then sends the request packet to the system memory device, which retrieves and returns the requested data. The interface may include a pair of buffers which store both the information requested by the CPU and speculative or prefetch information.

Abstract: An apparatus and system may include a peripheral device, such as an interrupt controller or Peripheral Component Interconnect (PCI) bridge device, having a memory-mapped legacy register and a PCI dummy register. The legacy register may be accessed by a Basic Input/Output System (BIOS) as part of a power-on initialization sequence for the peripheral device, and the dummy register may be accessed during a hot-plug operation using code executed by an Operating System (OS). An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a method of representing a peripheral device which includes identifying the peripheral device as a legacy device in a name space, such as an Advanced Configuration and Power Interface (ACPI) name space, and identifying the peripheral device as a dummy PCI device capable of being accessed during a hot-plug operation.

Abstract: Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Abstract: A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches is provided with a Pseudo Least-Recently-Used (PLRU) replacement algorithm to identify a least-recently-used (PLRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in the processor caches.

Abstract: A method includes determining the node ID information of a second node device of a multi-node computer system. The method stores the node ID information of the second node device on a storage device located on a first node device of the multi-node computer system. The first node device is connected to the second node device and the second node device includes a storage device containing node ID information for a third node device connected to the second node device.

Abstract: A multi-port switch is incorporated into a multi-node computer system and at least a first port of the multi-port switch is assigned to a first domain.

Abstract: A method and apparatus for the dynamic detection of graph-based connectivity among PCI (Peripheral Component Interconnect) devices are disclosed. A connectivity capability structure of a device and a list of connection records for the device are used to determine connectivity information for the device.

Abstract: An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.

Abstract: An interrupt method, system, and/or medium may comprise generating a load balancing value that helps balance servicing of interrupts among processors.

Abstract: Error methods, systems, and medium may comprise processing error conditions associated with transactions in a manner that may enable error source identification.

Abstract: One aspect of the invention relates to a method for supporting hibernation despite the presence of hot-plugged nodes and non-deterministic boot operations. The method comprises invoking a management interrupt in response to a Hibernate request. The management interrupt is used to obtain and store platform configuration information into a non-volatile storage location. The platform configuration information includes data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence as well as a boot node identifier and a listing of an order in which processors of the platform are initialized.