Patents by Inventor Lisa Fredrickson
Lisa Fredrickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9191029Abstract: An encoder provides (2t?1) redundant symbols in a sequence of n coded symbols, and a decoder corrects up to t erroneous symbols in the sequence of n coded symbols corrupted by a plurality of symbol errors. The decoder uses an improved decoding method, the method solving a plurality of matrix equations, each matrix equation associated with a hypothetical location of error. By monitoring a plurality of solutions associated with hypothetical locations of error, a processor determines the actual number of errors, the locations of the erroneous symbols in the sequence of n symbols, and the erroneous symbol value at each error location. The improved decoder includes erasure processing and a correct symbol determination method similar to erasure processing.Type: GrantFiled: June 29, 2014Date of Patent: November 17, 2015Inventor: Lisa Fredrickson
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Publication number: 20150007000Abstract: An encoder provides (2t?1) redundant symbols in a sequence of n coded symbols, and a decoder corrects up to t erroneous symbols in the sequence of n coded symbols corrupted by a plurality of symbol errors. The decoder uses an improved decoding method, the method solving a plurality of matrix equations, each matrix equation associated with a hypothetical location of error. By monitoring a plurality of solutions associated with hypothetical locations of error, a processor determines the actual number of errors, the locations of the erroneous symbols in the sequence of n symbols, and the erroneous symbol value at each error location. The improved decoder includes erasure processing and a correct symbol determination method similar to erasure processing.Type: ApplicationFiled: June 29, 2014Publication date: January 1, 2015Inventor: Lisa Fredrickson
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Publication number: 20140012889Abstract: Improved multiplier construction methods facilitate efficient multiplication in finite fields. Implementations include digital logic circuits and user scaleable software. Lower logical circuit complexity is achieved by improved resource sharing with subfield multipliers. Split-optimal multipliers meet a lower bound measuring complexity. Multiplier construction methods are applied repeatedly to build efficient multipliers for large finite fields from small subfield components. An improved finite field construction method constructs arbitrarily large finite fields using search results from a small starting field, building successively larger fields from the bottom up, without the need for successively larger searches. The improved method constructs arbitrarily large finite fields with limited construction effort using a polynomial constant equal to the product of a deterministic product term and a selectable small field scalar.Type: ApplicationFiled: July 4, 2012Publication date: January 9, 2014Inventor: Lisa Fredrickson
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Publication number: 20140013181Abstract: An improved error correction system, method, and apparatus provides encoded sequences of finite field symbols, each with a plurality of associated weighted sums equal to zero, and decodes encoded sequences with a limited number of corruptions. Each of the multiplicative weights used in the weighted sums is preselected from a smaller subfield of a large finite field. Decoding proceeds by determining multiplicative weights using various operations over the smaller subfield. When a limited number of corruptions occur, improved system design ensures that the probability of decoding failure is small. The method and apparatus extend to determine one or more decoding solutions of an underdetermined set of equations, including detection of ambiguous solutions.Type: ApplicationFiled: July 1, 2013Publication date: January 9, 2014Inventor: Lisa Fredrickson
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Patent number: 8145727Abstract: A real-time locater for digital media objects, related to one or more creative compositions and accessible over a network, is described. A service-provider maintains a master index of the digital media objects. The master index is organized by considering each media object to be an example of a primary attribute associated with the media object by a multitude of users. The reference is constructed as a data structure of primary attributes and means of locating the media objects as instances of primary attributes. Each such media object may be further categorized by associating it with one or more secondary attributes. The data structure is augmented to provide for efficient location of media objects by relating secondary attributes.Type: GrantFiled: October 10, 2007Date of Patent: March 27, 2012Assignee: YAHOO! Inc.Inventors: Roberto Warren Fisher, Lisa Fredrickson, Chris Kalaboukis, Ronald Martinez, Ian C. Rogers
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Publication number: 20090113301Abstract: A toolbar application for network browser applications is described. The tool augments web pages with related multimedia content. The browser application allows the user to locate and render a web page of personal interest. The tool invokes a mechanism to identify one or more media objects related to the web page in a playlist, and invokes a media object player application to render the one or more media objects in the playlist. When all of the media objects in the playlist are complete, the enhancement application may automatically generate one or more additional playlists.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: Yahoo! Inc.Inventors: Roberto Warren Fisher, Lucas Gonze, Eglia Nair Flores, Lisa Fredrickson, Chris Kalaboukis, Ronald Martinez, Ian C. Rogers
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Publication number: 20090113315Abstract: A method to provide additional media objects for two or more users intercommunicating over a network is described. The intercommunication messages are analyzed to determine additional related media objects available on the network, and one or more best related media objects are transmitted to the intercommunicating users. The additional media objects are rendered within the context of the network intercommunication.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: Yahoo! Inc.Inventors: Roberto Warren Fisher, Lucas Gonze, Eglia Nair Flores, Lisa Fredrickson, Chris Kalaboukis, Ronald Martinez, Ian C. Rogers
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Publication number: 20090100151Abstract: A real-time locater for digital media objects, related to one or more creative compositions and accessible over a network, is described. A service-provider maintains a master index of the digital media objects. The master index is organized by considering each media object to be an example of a primary attribute associated with the media object by a multitude of users. The reference is constructed as a data structure of primary attributes and means of locating the media objects as instances of primary attributes. Each such media object may be further categorized by associating it with one or more secondary attributes. The data structure is augmented to provide for efficient location of media objects by relating secondary attributes.Type: ApplicationFiled: October 10, 2007Publication date: April 16, 2009Applicant: Yahoo! Inc.Inventors: Roberto Warren Fisher, Lisa Fredrickson, Chris Kalaboukis, Ronald Martinez, Ian C. Rogers
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Publication number: 20070011592Abstract: A Reed Solomon decoder architecture. The architecture uses a modified version of the error-evaluator polynomial form proposed by Horiguchi, and later improved by Feng. The architecture is an improvement over Feng in that the area of the dominant PDU unit has been significantly reduced, while maintaining nearly the same iteration time, in novel slice circuitry which rotates terms to share a common multiplier and other circuitry. In addition, a novel implementation of storage of the B polynomial and associated overflow flags allows its storage to be minimized and provides equivalent functioning of the Chien search unit using a proprietary dual-multiplier arrangement in place of random multipliers used by Feng.Type: ApplicationFiled: August 17, 2006Publication date: January 11, 2007Inventors: Lisa Fredrickson, Leilei Song
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Patent number: 7123668Abstract: A simplified Viterbi detector for maximum likelihood detection of nine-bit QPSK symbols, employing a difference metric and two comparators, instead of using two state metrics and four comparators. The detector is used to process the outputs of synchronously sampled matched filters. A multiplexer is employed to select the difference metric from amongst the input sample, the fed back value of the difference metric itself, or the inverses of either, depending on decision signals output from the comparators, which in turn compare the difference metric with the input sample and it's inverse. The even path history then represents the most likely value of the detected symbol.Type: GrantFiled: September 23, 2002Date of Patent: October 17, 2006Assignee: Agere Systems Inc.Inventor: Lisa Fredrickson
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Patent number: 7117425Abstract: A Reed Solomon decoder architecture that uses a modified version of the error-evaluator polynomial form having a significantly reduced area of the dominant PDU unit, without loss in iteration time, in slice circuitry, which rotates terms to share a common multiplier and other circuitry. In addition, a B polynomial is stored, and associated overflow flags are implemented, to allow its storage to be minimized using a dual-multiplier arrangement. The decoder for error correcting codes comprises a syndrome calculation circuit, and a polynomial determining unit comprising slices, and a single multiplier in each of the slices, wherein each of the slices is employed a plurality of times in successive clock cycles. A correction circuit comprises a first multiplier employed when a scratch polynomial has overflowed, and a second multiplier employed when not overflowed.Type: GrantFiled: September 23, 2002Date of Patent: October 3, 2006Assignee: Agere Systems Inc.Inventors: Lisa Fredrickson, Leilei Song
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Patent number: 7082564Abstract: Reed-Solomon encoders providing support for multiple codes in a simple architecture having a reduced number of Galois field multipliers. Rather than implementing n subfilters each representing an individual degree polynomial filter as in conventional Reed-Solomon encoder, multiple degree polynomials are factored in a way which is convenient to a desired plurality of Reed-Solomon codes. Thus, not only are the number of required Galois field multipliers reduced, but support for different Reed-Solomon codes is provided with a minimized number of Galois field multipliers. Preferred embodiments in compliance with the proposed 802.16.1 wireless standard support up to sixteen Reed-Solomon codes all within a single architecture, including sixteen subfilters, either cascaded or in parallel. Each of the individual filters balances and reduces critical path lengths in the Reed-Solomon encoder, and reduces the loading of critical nets, resulting in a Reed-Solomon encoder with a greater throughput for a given technology.Type: GrantFiled: September 23, 2002Date of Patent: July 25, 2006Assignee: Agere Systems Inc.Inventors: Lisa Fredrickson, Bomey Yang
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Patent number: 6826723Abstract: The present invention provides for smaller, faster Reed-Solomon encoders, while at the same time providing support of multiple codes in a simple architecture having a reduced number of Galois field multipliers. In accordance with the principles of the present invention, a polynomial is factored differently than conventional Reed-Solomon encoders, resulting in enhanced performance, simplified circuitry, and/or a reduction of critical paths in the Reed-Solomon encoders. Thus, not only are the number of required Galois field multipliers reduced, but support for three different Reed-Solomon codes is provided with a minimized number of Galois field multipliers. In the disclosed embodiments, rather than implementing n subfilters each representing an individual degree polynomial filter as in Cox's conventional Reed-Solomon encoder, the present invention implements multiple degree polynomials factored in a way which is convenient to a desired plurality of Reed-Solomon codes.Type: GrantFiled: May 9, 2001Date of Patent: November 30, 2004Assignee: Agere Systems Inc.Inventor: Lisa Fredrickson
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Publication number: 20040059989Abstract: Reed-Solomon encoders providing support for multiple codes in a simple architecture having a reduced number of Galois field multipliers. Rather than implementing n subfilters each representing an individual degree polynomial filter as in Cox's conventional Reed-Solomon encoder, multiple degree polynomials are factored in a way which is convenient to a desired plurality of Reed-Solomon codes. Thus, not only are the number of required Galois field multipliers reduced, but support for different Reed-Solomon codes is provided with a minimized number of Galois field multipliers. Preferred embodiments in compliance with the proposed 802.16.1 wireless standard support up to sixteen Reed-Solomon codes all within a single architecture, including sixteen subfilters, either cascaded or in parallel.Type: ApplicationFiled: September 23, 2002Publication date: March 25, 2004Inventors: Lisa Fredrickson, Bomey Yang
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Publication number: 20040059991Abstract: A simplified Viterbi detector for maximum likelihood detection of nine-bit QPSK symbols, employing a difference metric and two comparators, instead of using two state metrics and four comparators. The detector is used to process the outputs of synchronously sampled matched filters. A multiplexer is employed to select the difference metric from amongst the input sample, the fed back value of the difference metric itself, or the inverses of either, depending on decision signals output from the comparators, which in turn compare the difference metric with the input sample and it's inverse. The even path history then represents the most likely value of the detected symbol.Type: ApplicationFiled: September 23, 2002Publication date: March 25, 2004Inventor: Lisa Fredrickson
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Publication number: 20040059990Abstract: A Reed Solomon decoder architecture. The architecture uses a modified version of the error-evaluator polynomial form proposed by Horiguchi, and later improved by Feng. The architecture is an improvement over Feng in that the area of the dominant PDU unit has been significantly reduced, while maintaining nearly the same iteration time, in novel slice circuitry which rotates terms to share a common multiplier and other circuitry. In addition, a novel implementation of storage of the B polynomial and associated overflow flags allows its storage to be minimized and provides equivalent functioning of the Chien search unit using a proprietary dual-multiplier arrangement in place of random multipliers used by Feng.Type: ApplicationFiled: September 23, 2002Publication date: March 25, 2004Inventors: Lisa Fredrickson, Leilei Song
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Publication number: 20030154440Abstract: The present invention provides for smaller, faster Reed-Solomon encoders, while at the same time providing support of multiple codes in a simple architecture having a reduced number of Galois field multipliers. In accordance with the principles of the present invention, a polynomial is factored differently than conventional Reed-Solomon encoders, resulting in enhanced performance, simplified circuitry, and/or a reduction of critical paths in the Reed-Solomon encoders. Thus, not only are the number of required Galois field multipliers reduced, but support for three different Reed-Solomon codes is provided with a minimized number of Galois field multipliers. In the disclosed embodiments, rather than implementing n subfilters each representing an individual degree polynomial filter as in Cox's conventional Reed-Solomon encoder, the present invention implements multiple degree polynomials factored in a way which is convenient to a desired plurality of Reed-Solomon codes.Type: ApplicationFiled: May 9, 2001Publication date: August 14, 2003Inventor: Lisa Fredrickson
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Patent number: 6493162Abstract: A method and apparatus for synchronizing a Viterbi detector to data frames corresponding to code words read from of a medium is provided.Type: GrantFiled: December 4, 1998Date of Patent: December 10, 2002Assignee: Seagate Technology LLCInventor: Lisa Fredrickson
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Patent number: 6470474Abstract: A method and apparatus are provided for identifying errors in a detected sequence of values generates the detected sequence of values from channel samples using a detector designed for a channel with a first channel response characteristic. The detected sequence of values is filtered using a filter that emulates a second channel response characteristic to produce a sequence of simulated second channel samples. The channel samples provided to the detector are also provided to a second filter which emulates a response characteristic equal to the second channel response characteristic divided by the first channel response characteristic. This produces a sequence of actual second channel samples. A sequence of difference values is then generated by subtracting each of the simulated second channel samples from a corresponding actual second channel sample. Using the sequence of difference values, at least one error is identified in the detected sequence of values.Type: GrantFiled: September 17, 1999Date of Patent: October 22, 2002Assignee: Seagate Technology LLCInventors: Lisa Fredrickson, Vladimir Kovner
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Patent number: 6400288Abstract: An encoder is provided that converts data words into code words. The code words, when concatenated together, are such that sub-strings of consecutive first symbols in the code words have no more symbols than a maximum number; sub-strings having the maximum number of consecutive first symbols and beginning at selected locations within the code words appear without restriction, and sub-strings having the maximum number of consecutive first symbols and beginning at locations other than the selected locations appear only where the sub-string is concatenated with an acceptable secondary sub-string. A method is also provided for generating a set of such code words for an encoder.Type: GrantFiled: September 17, 1999Date of Patent: June 4, 2002Assignee: Seagate Technology LLCInventors: Lisa Fredrickson, Anuradha Sukhija