Abstract: An encoder and a method of encoding successive data words into successive code words for transmission through a channel is provided. The encoder maps a first portion of each successive data word unchanged into a first portion of a corresponding one of the successive code words and maps a second portion of each successive data word into a second portion of a corresponding one of the code words according to a selected code. The successive code words are concatenated to form an encoded bit stream having a plurality of bit positions. The selected code imposes a run length constraint on the successive code words such that the encoded bit stream has a maximum possible run of ten consecutive binary zeroes in adjacent ones of the plurality of bit positions and imposes an interleave constraint on the selected code words such that the encoded bit stream has a maximum possible run of ten consecutive binary zeroes in every other one of the plurality of bit positions.

Abstract: A phase detector for a timing control loop provided in a signal sampling system to control taking samples by a sampler of input signals provided to a signal sampling system to result in a signal sample sequence output using a slope estimator and an error determiner with a phase error estimator combiner. The combiner output is provided to a summer directly and through a delay element to form phase error estimates.

Abstract: Signals indicative of unencoded input data are encoded into a plurality of encoded sequences. A first subset of the plurality of encoded sequences are encoded according to a k constrained code of rate x/y and a second subset of the plurality of unencoded sequences are encoded according to a k constrained code of rate m/n wherein x/y≠m/n. The encoded sequences are transmitted to a partial response channel subject to noise. The encoded sequences are transmitted from the channel to a Viterbi detector having a trellis structure with a preselected, time-dependent pattern to create a time varying trellis structure for limiting a maximum length of parallel paths therethrough. The encoded sequences are detected with a Viterbi detector to provide detected, encoded sequences. The detected, encoded sequences are then decoded to provide an estimate of the input data.

Abstract: In a peak detection system having a variable gain amplifier (VGA), a counter is initialized and a countdown is triggered. Each time a qualified peak is detected, the counter is re-initialized. If the countdown is completed, the VGA gain is updated. This method can be used to boost amplifier gain that is too low to generate a qualifying threshold, even while overlooking short periods of very low output.

Abstract: A Viterbi PRML system and method providing a new code with distance properties such that some tribits are allowed but no longer sequences are allowed. A code rate 8/ 9 is constructed for EPR4 and E.sup.2 PR4 channels and the system independently maps 8-bit blocks of user data to 9-bit channel sequences. The precoder has transfer function, f(D)=1/(1.sym.D), and produces a binary channel input x(D), which is fed to a coder, to provide an output signal y(D), which is transmitted and corrupted by noise. The corrupted signal is received and fed to a Viterbi detector. The signal is decoded to produce an estimate of the 8-bit data bytes, as reconstructed to be freed from noise corruption. The encoding protocol of the invention is implemented in the encoder.

Abstract: A data symbol sequence detector for choosing data symbol sequences likely to be represented by corresponding sequences of samples received by the detector with these sample sequences formed by sampling data signals obtained from magnetically stored data through a data retrieval channel which asymmetrically affects the magnitudes of the data signals. An expected sample value estimator provides estimated expected magnitude values for a selected set of samples in the sequence, and a magnitude difference determiner is used for obtaining representations of differences between values of the samples in the sequence and the corresponding estimated expected values. These differences representations can be limited in algebraic form.

Abstract: A digital peak detection system digitizes analog signals and provides absolute values to a series of one cycle delays, and to a sequence of comparator stages. Each digital sample is parallel compared to a number of preceding samples equal to the number of active comparator stages. Control signals activate comparator stages to determine sample comparison window length, including lengths exceeding the number of samples between recorded peaks. Peak detection is optimized using a variable gain amplifier whose gain is updated based upon amplitude difference between actual and desired peak samples. When sample amplitudes are smaller than a qualifier threshold, a countdown timer increases amplifier gain after lapse of a programmed time without detecting a qualified pulse. Gain is also updated when the analog to digital converter saturates. Initial gain values can be programmed, and gain stored at the end of a servo mode for future use in reducing gain control loop convergence time.

Abstract: A signal conditioning system for controlling characteristics of an analog signal obtained from magnetically stored data through a data retrieval channel that asymmetrically affects analog signal magnitudes. Errors in samples are segregrated by association with intended sample values, and the different segregates are used in selected versions in control loops to control selected characteristics of the analog signal.

Abstract: According to the invention, a data integrity code including logical block address ("LBA") and circuit implementation are provided. The code and implementing circuitry are utilized to enable data block LBA verification during a block transfer and retrieval process. The preferred data integrity code has embedded LBA information and also serves as a crosscheck code used to detect miscorrection by an error correction code ("ECC"). In a preferred disk drive embodiment, data integrity block ("DIB") is provided to verify that the LBA value associated with a given data block in a host interface matches the value associated with that same data block in a buffer memory and in a data sequencer. In a preferred method of use, data integrity/cross-check redundancy with LBA is appended to data blocks transmitted to a buffer memory and verified after the data block has been transferred from the buffer.

Abstract: An encoder for matched spectral null binary codes is described, particularly for 12B/15B codes. The codeword trellis is partitioned into two or more subtrellises, and each subtrellis is encoded separately. The codeword is the concatenation of the codewords produced by the subtrellises. Some valid sequences have to be excluded, in order to ensure that all concatenations are valid, but the storage requirements, are greatly reduced.

Abstract: A system architecture for implementing a 10-bit Reed-Solomon code for detecting and correcting data errors in a single code word to protect a data block containing up to 1023 10-bit data symbols, i.e., the equivalent of up to 1278 8-bit symbols, including error check redundancy, maximizes the use of all allocated error correction overhead for an entire block of data, regardless of the particular error pattern characteristics encountered in a given system application. The architecture is particularly well suited for digital data processing and/or storage systems encountering non-bursty, (i.e., substantially random), error patterns, such is characteristic of data storage and retrieval systems employing semiconductor based memory stores. 5-bit extension field operations, (i.e., over a Galois field GF(2.sup.5)), generated by using the irreducible polynomial, P.sub.32 (X)=X.sup.5 +X.sup.2 +1, over GF(2), are utilized to perform certain, requisite arithmetic functions over the Galois field GF(2.sup.

Abstract: A word-wise encoder circuit that processes word formatted data blocks in response to a word clock signal and generates redundancy in accordance with an 8 bit symbol code. The encoder is provided with two parallel data paths, each receiving one of the respective bytes halves of the received data words during one word clock period to implement an 8 bit symbol code in response to a word clock signal. The word-wise encoder replicates, in one word clock period, the state of the registers in a standard sequential encoder after two consecutive bytes have been processed in response to a byte clock. In a preferred embodiment, a word-wise encoder is used to implement a Reed-Solomon data integrity code. In this example, the word-wise encoder generates redundancy that is appended to associated data blocks temporarily stored in a block buffer memory within a data channel to provide a mechanism for detecting data errors caused by the buffer.

Abstract: A digital communication apparatus transmits sectors of digital values that include error correction values used to detect and correct errors within the sector. Each sector consists of a number of blocks and the error correction values of each block are useful in correcting up to a maximum number of erroneous digital units in that block. The digital communication apparatus encodes the blocks of digital units to transmit them through a channel and then decodes the channel's representation of those encoded blocks, where the channel's representation occasionally contains burst errors. The encoding and decoding is performed in a manner that reduces the number of consecutive erroneous digital units caused by any one burst error to a number less than the number of blocks in a sector, ensuring that the error burst corrupts at most one digital unit in each block.

Abstract: A method and means for detecting spectral null sequences of a spectrally-constrained code at the output of a noisy communications channel by tracking the spectral content of said sequences with a Viterbi detector using an N stage trellis and mapping each spectral null sequence to a unique path of acyclic successive states and edges through said trellis by selectively outsplitting counterpart states at preselected times modulo N in said trellis such that no pair of unique paths support the same spectral null sequence.

Abstract: Maximum likelihood detection of a trellis code using a Viterbi detector constructed from a time-varying trellis structure that is associated with a partial response channel and consists of connected trellises with periodically repeated patterns of nodes and subtrellises of said trellises. Each subtrellis has nodes representing a current state of the channel and value of a predetermined tracked attribute. A survivor metric and a survivor sequence from a node at the end of one subtrellis are reassigned to a node at the beginning of an adjacent subtrellis having a different value of the tracked attribute for increasing minimum distance properties, reducing error event length and improving code constraints for timing and gain control. The one subtrellis and adjacent subtrellis may be within a single trellis or in adjacent trellises.

Abstract: A method for constructing trellis codes and an apparatus for providing trellis codes with increased minimum distance between output sequences of partial response channels with constrained inputs. A Viterbi detector expands a conventional trellis structure for the channel incorporating additional states interconnected such that a preselected function associates each state in the trellis with an algebraic evaluation of a polynomial at a particular element of a finite field. The detector trellis is time-varying such that only certain values of the preselected function are allowed every m bits. The time-variation assures that there are no minimum distance extensions of erroneous sequences beyond a predetermined length in the trellis. Reliability of storage channels is desirably increased, because more noise is required to overcome the additional distance and cause an error in distinguishing the correct encoded sequence.