Abstract: A mixed technology microcircuit including a first circuit fabricated on a first layer with a first technology and a second circuit fabricated on a second layer with a second technology. In the illustrative embodiment, the first circuit is fabricated with silicon germanium (SiGe) technology and the second circuit is fabricated with complementary metal-oxide semiconductor (CMOS) technology. In an illustrative application, the first circuit includes a high-speed data receiver and a high-speed data transmitter. In the illustrative implementation, the data receiver includes a line receiver, a data and clock recovery circuit, and a demultiplexer and the data transmitter includes a multiplexer, a data and clock encoding circuit, and a line driver.

Abstract: An apparatus for selectably converting emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL) signals to negative complimentary metal oxide semiconductor (NCMOS) signals is disclosed. The apparatus uses an input level shifter, a secondary level shifter, and an output buffer to convert the ECL and PECL differential signals to single-ended signals. The apparatus also includes a disable output function for disabling the output of the output buffer. The apparatus may be integrated multiple times on a substrate containing NCMOS circuitry, thereby allowing the NCMOS circuitry to be driven by differential signals. Alternatively, the present invention may be integrated multiple times onto a single substrate to create a dedicated universal translator.

Abstract: A low noise, low distortion radio frequency amplifier which includes a bootstrap design to minimize intermodulation distortion while simultaneously achieving low noise and wide bandwidth. In the illustrative embodiment, the invention includes a first circuit for receiving an input signal; a second circuit for amplifying the input signal using a transistor Q2; and a third circuit for regulating a rate of change of voltage across the transistor Q2 such that the rate of voltage change is zero. The third circuit includes a transistor Q3 connected to the transistor Q2 in cascode. In the specific illustrative embodiment, the third circuit further includes two diodes D1 and D2 used to modulate the voltage at the input of the transistor Q3 in proportion to the voltage modulation at the input of the transistor Q2. In the illustrative embodiment, the second circuit includes a transistor Q1 connected in cascade to the transistor Q2.

Abstract: A system and method for effecting wideband image rejection. In a receiver implementation, the inventive method includes the steps of receiving a first signal in a first frequency band and generating in-phase and quadrature signals therefrom. The phase of the in-phase signal is shifted to provide a second signal and the phase of the quadrature signal is shifted to provide a third signal. A predetermined phase relationship is thereby effected between the second and the third signals. The second and third signals are then summed to provide an output signal which has minimal interference from a mixing signal. In an illustrative receiver application, the phase shifting is achieved via the use of all pass networks. Each of the all pass networks include a differential amplifier having first and second input terminals. The first and the second terminals are connected to a first end of first and second resistive elements, respectively.

Abstract: An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out.

Abstract: A transceiver has a digital signal processor which can insert calibration signals of known level and frequency into transmitters for calibration and correction of transmitter parameters. An output of the calibrated and corrected transmitter is subsequently coupled into a calibration mixer along with a mixing signal (e.g., from a local oscillator generator. The outputs of the calibration mixer have known levels and frequencies and are inserted into receivers for calibration and correction of receiver parameters.

Abstract: A "gain control differential pair" (GCDP) conducts current in response to a differential drive signal, with the gain of a signal path formed via the current circuit of one of its transistors controlled by the drive signal. The GCDP is preferably driven with a drive circuit that receives a symmetrical input signal and produces an offset differential drive signal which has the effect of keeping one of the GCDP's transistors turned off over a wider portion of a symmetrical input signal's voltage range, thereby reducing GCDP-caused noise. One or more GCDPs are implemented as part of a Gilbert mixer to regulate the amount of RF current that flows between the mixer's output and input stages, which eliminates the need to provide gain control in other circuits fed by the mixer. When driven with an offset drive signal, the Gilbert mixer simultaneously provides gain control, low distortion, low power consumption and excellent LO/RF isolation.

Abstract: A dither circuit is monolitically integrated with a subranging ADC to add a dither signal at the input of the ADC's fine quantizer element to randomize its nonlinear quantization level errors. Because the subranging ADC has at least one overlap bit, the amplitude of the dither signal can range up to at least 2.sup.M-1 LSBs of the fine quantizer without saturating it. The digital equivalent of the dither signal is subtracted at the output of the fine quantizer to maintain the ADC's overall SNR. The randomization of only the fine quantizer element avoids gaining up the nonlinear errors associated with the dither signal itself thereby improving the overall SNR. This approach optimizes performance for small input signals while sacrificing flexibility to correct other sources of error.

Abstract: In a subranging ADC, the unary DAC is trimmed by walking through its transfer function while toggling an offset cell at the input to the coarse quantizer and a reference cell in the DAC such that the reference cell is substituted for the cell under test on alternating cycles to provide the last lsb of the reconstructed signal. A test circuit measures the voltage at the output of the summing amplifier for both conditions and generates an error voltage in which the common mode terms have been rejected. The cell under test is then laser trimmed to reduce the error voltage until the cell's DNL error is within an error bound of a tolerance. In one embodiment, the tolerance is dithered to improve spur free dynamic range.

Abstract: A monolithic class AB (push-pull) low noise amplifier having feedback and self bias. The low noise amplifier exhibits low power, high intercept point, low noise figure, well matched terminal impedances over wide range of frequency, and may be monolithically implemented. The amplifier may be produced using CMOS process technologies. The amplifier comprises NMOS and PMOS transistors serially coupled between a voltage rail and ground. The amplifier uses self biasing embodied in a bias resistor coupled between an input shunt capacitor and respective drains of the NMOS and PMOS transistors, which allows for maximum gate-to-source voltage and higher transconductance for a minimum aspect ratio (W/L). This results in a wider bandwidth and reduced power for the amplifier.

Abstract: A low voltage analog front end (AFE) includes a differential transistor pair which converts an input voltage, typically A.C.-coupled to the pair's control inputs, to a differential current. Impedance networks connected to each transistor's control input are joined together at a common node, and a current source is connected to the node which causes DC bias currents to be mirrored through the pair's current circuits, so that the AFE's differential output current comprises a differential current produced by the pair in response to an input voltage and superimposed on the DC bias currents. The current source preferably generates mirrored currents which are larger than its reference current to linearize the pair's response and to provide the AFE with a wide dynamic range. An input to the AFE sees a low impedance which is about equal to the sum of the impedance networks, which can be resistive or complex as needed.

Abstract: Mixer structures are described which include a current mirror for insertion of trickle currents to an input differential amplifier and an output interface for coupling an output differential amplifier to an output port. The current mirror trickle currents improve the mixer's conversion gain and third-order intercept point and the current mirror introduces them without introducing spurious signals. The output interface couples mixer currents to the output port while isolating the output port from power-supply spurious signals.

Abstract: A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.

Abstract: An amplifier includes an amplifying circuit and bias current circuit. The bias current circuit includes a beta matching circuit which employs a temperature compensated current reference to develop a bias current for the amplifying circuit. The beta matching circuit is connected to track the current gains of transistors within the amplifying circuit and to thereby provide a temperature compensated bias current to the amplifying circuit. The bias current maintains a fixed bias point regardless of temperature-induced, or other, variations of the current gains of the amplifying circuit's transistors.

Abstract: A low-noise, low-distortion clamping scheme includes a bootstrapped voltage clamp and an R.sub.gm current clamp that provide superior overdrive protection when used together in a Class-AB feedback amplifier. The bootstrapped voltage clamp includes a transistor that is connected to a circuit node to be clamped. The transistor's base is bootstrapped to the node to maintain a constant V.sub.be when not clamping, to reduce the adverse effects of the junction capacitance C.sub.je which would normally vary with the node voltage and distort the signal at the node. Two such clamps provide positive and negative voltage limiting. The R.sub.gm current clamp is used in the input stage of a Class-AB feedback amplifier to limit the current through the resistor R.sub.gm that interconnects the current inputs of two transconductance amplifiers whenever the voltage drop across R.sub.gm increases to an unacceptable level.

Abstract: A power supply terminal clamping circuit for use in an integrated circuit protects positive and negative voltage power supply terminals from both overvoltage and ESD events. A diode stack is connected between a protected power supply terminal and ground, with the number of diodes in the stack establishing a clamping voltage. The stack becomes forward-biased when the voltage on the protected terminal reaches the clamping voltage, which triggers a switch that provides a current path between the terminal and ground that clamps the terminal voltage. A bipolar transistor embodiment includes a diode stack made from diode-connected bipolar transistors and a bipolar Darlington pair switch.

Abstract: A non-attenuating automatic variable gain amplifier (VGA) circuit includes an operational amplifier (op amp) with a feedback resistor connected between its output and inverting input terminals. A variable gain setting resistance circuit having a variable resistance is the gain setting resistor positioned between the op amp's inverting input and a low voltage supply. By varying the resistance of the variable resistance circuit, the gain of the VGA circuit can be manipulated without requiring attenuation of the input signal. A resistance setting control for the variable resistance circuit can operate open loop, fed back from the amplifier output, or fed forward from the amplifier input.

Abstract: A bias voltage source (20) produces a variable bias voltage (VBREF) which regulates the bias currents in an array (30) of transistor current switch cells (34,36) in an digital-to-analog converter (DAC). The bias voltage (VBREF) is applied to the bases of the regulating transistors (Q8') in the cells (34,36) to regulate the bias currents in their respective main transistors (Q6',Q7') to values proportional to the main bias current (IBIAS). Each main transistor (Q6,Q6',Q7,Q7') and regulating transistor (Q8,Q8') is provided with a compensating transistor (Q10,Q10')(Q11,-Q11') which sinks the emitter-base current thereof and cancels deviation of the actual current gain from the design current gain. Another compensating transistor (Q9,Q9') is connected to each regulating transistor (Q8,Q8') to cancel the effect of base-emitter voltage variation with temperature.

Abstract: Switching between two logic circuits that produce outputs at different respective logic levels is accomplished by means of a common input differential switch that has a branch in each logic circuit. A common current source supplies current to the branches within each logic circuit. The current source remains on regardless of which logic level is selected, thereby enhancing switching speed. The logic circuits produce logic outputs at a common output differential switch, which in turn provides a selected output to a single output terminal. The logic circuits are configured so that the output from the circuit corresponding to the selected logic level dominates the output from the other logic circuit at the output differential switch.

Abstract: First and second current feedback transconductance amplifiers (102,104) each have a high impedance voltage input, a low impedance current input and a pair of push-pull current outputs. In a single-ended configuration, an input signal is applied to the voltage input of the first transconductance amplifier (102) and the push-pull outputs of the both transconductance amplifiers are connected through a current mirror (136,138) to a node (134) where the current outputs are summed. The node current is integrated by a capacitor (174) to produce a voltage which is amplified by a transimpedance amplifier (190) to produce an output voltage which is fed back to the voltage input of the second transconductance amplifier (104). The current inputs of the transconductance amplifiers (102,104) are interconnected by a resistor (132). The high impedance voltage inputs produce common-mode cancellation of distortion in the transconductance amplifiers (102,104) and low input shot noise.