Abstract: A transconductance push-pull amplifier (20) generates primary push-pull currents (I1, I2) corresponding to a voltage input signal (VIN). Current mirrors (42,44) generate secondary push-pull currents (I3, I4) corresponding to the primary push-pull currents (I1, I2). For sampling, both the primary and secondary push-pull currents (I1, I2, I3, I4) are applied to charge a capacitor (C3) in a current feed-forward arrangement with high slew rate and fast signal acquisition to produce a voltage output signal (VOUT). The capacitor (C3) is disconnected from the amplifier (20) and current mirrors (42,44) to hold the output signal (VOUT). Switching transistors (Q13, Q15) which are connected between the capacitor (C3) and the current mirrors (42,44) have substantially the same non-linear modulation characteristics as corresponding output transistors (Q7, Q8) in the amplifier (20).

Abstract: A sample and hold circuit uses a Class AB amplifier architecture rather than a diode bridge in a sampling gate. Input and output transistor pairs (Q5, Q6; Q7, Q8) receive an input voltage (Vin) and provide at an output terminal (6) (a) an output voltage that tracks the input signal, and (b) a current from a load dependent current source (Vcc, Vee). The output current used to charge a sample holding capacitor (Ch) is not limited to the input standing current, and operates with a lower quiescent power consumption and better distortion than prior circuits. Complementary bipolar transistors (Q15, Q16, Q17, Q18; Q9, Q10, Q11, Q12) are used in a clock driver circuit and in the sampling gate to compensate for the different operating speeds of the npn and pnp transistors.

Abstract: A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin+V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation .DELTA.Vce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current .DELTA.Iload which is equal and opposite to the load current variation caused by a change (.DELTA.Vin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation .DELTA.Vbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (.DELTA.

Abstract: A diode bridge includes a plurality of diodes for coupling an input voltage signal to a holding capacitor for sampling when the diodes are forward biased, and uncoupling the voltage signal from the capacitor for holding when the diodes are reverse biased. The diode bridge has first and second bias current nodes. A constant current drain causes a constant bias current to flow out of the bridge. A transistor connects the first node to the drain for forward biasing the diodes, whereas a transistor connects the second node to the drain for reverse biasing the diodes. A bootstrap amplifier (A2) produces a variable control voltage which controls a pair of voltage-controlled constant current sources to cause the constant bias current to flow therethrough into the bridge. A transistor (Q7) couples the control voltage to the first current source for forward biasing the diodes, whereas a transistor couples the control voltage to the second current source for reverse biasing the diodes.

Abstract: A bandgap reference voltage source (104) has positive and negative terminals (104a,104b) which are connected through high impedance constant current sources (124c,126c) to positive and negative voltage supplies (+VDD,-VEE) respectively. The effect of variations of the voltage supplies (+VDD, -VEE) on the voltage source (104) is low due to the high impedances of the currents sources (124c,126c), providing a high power supply rejection ratio (PSRR). The reference voltage (VREF) generated by the voltage source (104) is converted into a reference current (IREF) which flows through two equal series resistors (108,110), and also through current mirrors (124,126) which produce positive and negative output currents corresponding thereto. The current sources (124c,126c) for the voltage source (104) are also controlled by the current mirrors (124,126).

Abstract: A diode bridge (12) includes a plurality of diodes (D1,D2,D3,D4) for coupling an input voltage signal (Vin) through a resistor (RH) to a holding capacitor (CH) for sampling when the diodes (D1,D2,D3,D4) are forward biased, and uncoupling the voltage signal (Vin) from the capacitor (CH) for holding when the diodes (D1,D2,D3,D4) are reverse biased. A constant current drain (S1) causes a constant bias current (IBIAS) to flow out of the bridge (12) through first and second bias current nodes (N1,N2) to a voltage source (VEE). The nodes (N1,N2) are also connected through current source resistors (R1,R2) to a voltage source (VCC). A first current regulator (72) is bootstrapped to the input signal (Vin) and regulates first and second bias currents flowing into the nodes (N1,N2) to constant values (IBIAS/2) to compensate for resistive current source modulation.

Abstract: A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin+V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation .DELTA.Vce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current .DELTA.Iload which is equal and opposite to the load current variation caused by a change (.DELTA.Vin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation .DELTA.Vbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (.DELTA.