Patents by Inventor Long-Ching Wang
Long-Ching Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096768Abstract: A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly connected to an exposed bottom surface of the end paddle. A longitudinal direction of an exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads. An entirely of each of the one or more Vin leads is of the full thickness.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Lin Chen, Long-Ching Wang, Hui Ye
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Publication number: 20230420340Abstract: A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie bar, the second tie bar, the third tie bar, and the fourth tie bar is not plated with the metal. A method for fabricating a semiconductor package includes the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, applying a trimming process, applying a plating process, and applying a singulation process.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Xiaoguang Zeng
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Patent number: 11784141Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.Type: GrantFiled: October 5, 2022Date of Patent: October 10, 2023Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Jun Lu, Long-Ching Wang, Madhur Bobde, Bo Chen, Shuhua Zhou
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Publication number: 20230307325Abstract: A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 ?m to 35 ?m. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Lin Lv, Shuhua Zhou, Long-Ching Wang, Jun Lu
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Patent number: 11721665Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.Type: GrantFiled: May 20, 2022Date of Patent: August 8, 2023Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Bo Chen
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Patent number: 11699627Abstract: A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.Type: GrantFiled: February 26, 2021Date of Patent: July 11, 2023Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Long-Ching Wang, Hongyong Xue, Madhur Bobde, Zhiqiang Niu, Jun Lu
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Publication number: 20230215783Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Long-Ching Wang, Xiaoguang Zeng, Mary Jane R. Alin, Hailin Zhou, Guobing Shen
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Patent number: 11581195Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.Type: GrantFiled: December 21, 2020Date of Patent: February 14, 2023Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Long-Ching Wang, Lei Fukuda, Adrian Chee Heong Koh, Peter Wilson, Feng Ye
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Publication number: 20230021687Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.Type: ApplicationFiled: October 5, 2022Publication date: January 26, 2023Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Jun Lu, Long-Ching Wang, Madhur Bobde, Bo Chen, Shuhua Zhou
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Patent number: 11495548Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.Type: GrantFiled: December 30, 2020Date of Patent: November 8, 2022Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Jun Lu, Long-Ching Wang, Madhur Bobde, Bo Chen, Shuhua Zhou
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Publication number: 20220278076Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.Type: ApplicationFiled: May 20, 2022Publication date: September 1, 2022Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Bo Chen
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Publication number: 20220278009Abstract: A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Long-Ching Wang, Hongyong Xue, Madhur Bobde, Zhiqiang Niu, Jun Lu
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Patent number: 11430762Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.Type: GrantFiled: December 30, 2020Date of Patent: August 30, 2022Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Bo Chen
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Publication number: 20220208724Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Bo Chen
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Publication number: 20220199425Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Long-Ching Wang, Lei Fukuda, Adrian Chee Heong Koh, Peter Wilson, Feng Ye
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Patent number: 11309233Abstract: A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.Type: GrantFiled: February 25, 2020Date of Patent: April 19, 2022Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, Jr., Long-Ching Wang, Jian Yin
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Patent number: 11258270Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.Type: GrantFiled: June 28, 2019Date of Patent: February 22, 2022Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
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Patent number: 11222858Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.Type: GrantFiled: June 19, 2020Date of Patent: January 11, 2022Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Xiaotian Zhang, Zhiqiang Niu
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Publication number: 20210398926Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.Type: ApplicationFiled: June 19, 2020Publication date: December 23, 2021Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Xiaotian Zhang, Zhiqiang Niu
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Patent number: 11101137Abstract: A process is applied to develop a plurality of reverse conducting insulated gate bipolar transistors (RCIGBTs). The process comprises the steps of providing a wafer, applying a first grinding process, patterning a mask, applying an etching process, removing the mask, implanting N++ type dopant, applying a second grinding process forming a TAIKO ring, implanting P+ type dopant, annealing and depositing TiNiAg or TiNiVAg, removing the TAIKO ring, attaching a tape, and applying a singulation process. The mask can be a soft mask or a hard mask. The etching process can be a wet etching only; a wet etching followed by a dry etching; or a dry etching only.Type: GrantFiled: March 19, 2020Date of Patent: August 24, 2021Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Zhiqiang Niu, Long-Ching Wang, Yueh-Se Ho, Lingpeng Guan, Wenjun Li