Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.

Abstract: An interconnected base plate comprises a metal layer, a plurality of metal pads, and a molding encapsulation. The mold compound layer encloses a majority portion of the plurality of metal pads 240. A respective top surface of each of the plurality of metal pads is exposed from a top surface of the molding encapsulation. The respective top surface of said each of the first plurality of metal pads and the top surface of the mold compound layer are co-planar. A power module comprises the interconnected base plate, a plurality of chips, a plurality of bonding wires, a plurality of terminals, a plastic case, and a module-level molding encapsulation. A method, for fabricating an interconnected base plate, comprises the steps of forming a plurality of metal pads; loading a metal layer; forming a molding encapsulation; and applying a singulation process.

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.

Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.

Abstract: A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.

Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.

Abstract: A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.

Abstract: A power semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a first metal clip, a second metal clip, an inductor assembly, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. A method for fabricating a power semiconductor package. The method comprises the steps of providing a lead frame; attaching a low side FET and a high side FET to the lead frame; mounting a first metal clip and a second metal clip; mounting an inductor; forming a molding encapsulation; and applying a singulation process.

Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.

Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.

Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Abstract: Embodiments provide a packaging arrangement that includes a high density interconnect bridge for interconnecting dies within the packaging arrangement. The packaging arrangement comprises one or more redistribution layers and an interconnect bridge embedded within the one or more redistribution layers. A first die is coupled to (i) a first portion of the one or more redistribution layers and (ii) a first portion of the interconnect bridge. A second die coupled to a (ii) a second portion of the one or more redistribution layers and (ii) a second portion of the interconnect bridge to electrically couple the first die and the second die via at least the first interconnect bridge.

Abstract: The present disclosure describes apparatuses and techniques for self-aligning integrated circuit (IC) dies. In some aspects, a hydrophobic material is deposited on a surface of a substrate to form a pattern on the surface of the substrate. The pattern may expose areas of the substrate surface for placement of IC dies. A water-based solution is then applied to the exposed areas such that droplets form on the exposed areas of the substrate surface. IC dies are placed on the droplets of the water-based solution, which can cause the IC dies to align with the exposed areas of the substrate surface. The droplets are then caused to evaporate such that the IC dies settle on the exposed areas of the substrate surface.

Abstract: A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.

Abstract: Embodiments include a semiconductor package comprising a first die having (i) a first side and (ii) a second side, wherein the first die comprises a first plurality of bond pads formed on the first side of the first die; a second die having (i) a first side and (ii) a second side, wherein the second die comprises a second plurality of bond pads formed on the first side of the second die, wherein the second die is stacked on the first die; a first plurality of metal posts formed on the first plurality of bond pads; a second plurality of metal posts formed on the second plurality of bond pads; and a redistribution layer configured to electrically couple (i) a first metal post of the first plurality of metal posts and (ii) a second metal post of the second plurality of metal posts.

Abstract: The present disclosure describes apparatuses and techniques for self-aligning integrated circuit (IC) dies. In some aspects, a hydrophobic material is deposited on a surface of a substrate to form a pattern on the surface of the substrate. The pattern may expose areas of the substrate surface for placement of IC dies. A water-based solution is then applied to the exposed areas such that droplets form on the exposed areas of the substrate surface. IC dies are placed on the droplets of the water-based solution, which can cause the IC dies to align with the exposed areas of the substrate surface. The droplets are then caused to evaporate such that the IC dies settle on the exposed areas of the substrate surface.

Abstract: Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs.

Abstract: Embodiments provide a packaging arrangement that includes a high density interconnect bridge for interconnecting dies within the packaging arrangement. The packaging arrangement comprises one or more redistribution layers and an interconnect bridge embedded within the one or more redistribution layers. A first die is coupled to (i) a first portion of the one or more redistribution layers and (ii) a first portion of the interconnect bridge. A second die coupled to a (ii) a second portion of the one or more redistribution layers and (ii) a second portion of the interconnect bridge to electrically couple the first die and the second die via at least the first interconnect bridge.