Abstract: A sequence of input groups, each input group containing a number of input pixels, is received. A sequence of output frames is provided, where each output frame contains a number of output pixels to refresh a display screen. The pixels of each output frame include (1) a number of new pixels which are the input pixels of a respective input group, and (2) a number of old pixels which are the input pixels of a previous input group. The previous input group is one that's received previous to the respective input group.

Abstract: A memory subsystem that includes a dynamic random-access memory (DRAM) having cells organized as an array of rows and columns, the cells being individually accessed by specifying a row address and a column address. An additional cell that stores a charge level is associated with each row of the DRAM. The charge level is characteristic of the charge level of the associated DRAM row, and is refreshed by a secondary or primary refresh cycle to the associated DRAM row. A threshold detector outputs a refresh signal when the charge of the additional cell drops below a predetermined threshold. Circuitry responsive to the refresh signal collects the row address of the additional cell and sends it to logic that generates a primary refresh cycle to the associated row address of the DRAM.

Abstract: In the system of the present invention an individual displayed pixel is a weighted combination of a video pixel and a graphics pixel. For example, a pixel displayed on a monitor may be three-quarters graphics and one-quarter video. In this system a color lookup table providing a red, a green and a blue lookup table output value is extended to provide a further lookup table output value. The further lookup table output value is a weight value representative of the relative weights of a video pixel and a corresponding graphics pixel. The weight value is applied to a matrix multiplier which also receives video pixel information and graphics pixel information. The matrix multiplier determines a weighted combination of the video and graphics pixel information according to the weight value to provide a blended pixel. A YUV standard to RGB standard conversion matrix is provided within in order to receive video signals in a YUV format and apply the video signals to the matrix multiplier in an RGB format.

Abstract: Visual data in a first color format stored in first memory locations are merged with visual data in a second color format, which different from the first color format, stored in second memory locations to form a merged pixel stream. An analog signal is generated representative of the merged pixel stream. In a preferred embodiment, one set of visual data is graphics data in an 8-bit CLUT format and the other set is video data in an 8-bit packed YUV9 format (also known as the 4:1:1 format). In this embodiment, the video data is unpacked and chromakeying is applied to generate the merged pixel stream.

Abstract: In the system of the present invention an individual displayed pixel is a weighted combination of a video pixel and a graphics pixel. For example, a pixel displayed on a monitor may be three-quarters graphics and one-quarter video. In this system a color lookup table providing a red, a green and a blue lookup table output value is extended to provide a further lookup table output value. The further lookup table output value is a weight value representative of the relative weights of a video pixel and a corresponding graphics pixel. The weight value is applied to a matrix multiplier which also receives video pixel information and graphics pixel information. The matrix multiplier determines a weighted combination of the video and graphics pixel information according to the weight value to provide a blended pixel. A YUV standard to RGB standard conversion matrix is provided within in order to receive video signals in a YUV format and apply the video signals to the matrix multiplier in an RGB format.

Abstract: A method and video camera for generating time varying video images. A first capture signal is received from a video processing system by a video camera, which captures a first set of one or more video frames in response to the first capture signal and transmits the first set of one or more video frames to the video processing system.

Abstract: A method and video processing system for receiving and processing consecutive sets of video signals from a video camera. A first capture signal is transmitted to the video camera. A first set of one or more video frames is received from the video camera in response to the first capture signal. The first set of one or more video frames is processed by the video processing system.

Abstract: A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found.

Abstract: Scalable platform architecture includes a high bandwidth bus for transmitting data at high bit rates between various video processing subsystems. A graphics processing subsystem, having graphics memory, is coupled to the high bandwidth bus. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The high bandwidth bus is provided with expansion connectors for detachably coupling to various subsystems. These subsystems may include a video processing subsystem and a video capture system. The high bandwidth bus is also provided with a bus bridge for coupling the high bandwidth bus to a low bandwidth bus or a central processing unit bus.

Abstract: A method and apparatus for processing signals for display using a single frame buffer. In a preferred embodiment, a plurality of pixels are received, wherein one or more of the plurality of pixels corresponds to a first display and one or more of the plurality of pixels corresponds to a second display. A display bit map and a display mask are generated in accordance with the plurality of pixels. If a pixel of the plurality of pixels corresponds to the first display and a corresponding mask field of the display mask has a first-display value, then the pixel is stored in the display bit map, wherein the mask field comprises at least one mask bit. Otherwise, if the pixel corresponds to a key color, then the mask field corresponding to the pixel is set to the first-display value. Otherwise, the pixel is stored in the display bit map and the mask field corresponding to the pixel is set to a second-display value.

Abstract: A graphics controller concurrently reads two streams of visual data stored in memory, where one of the streams is in a subsampled data format. The graphics controller upsamples the subsampled visual data and merges the two data streams to generate a merged pixel stream for display. One data stream may be graphics data in an 8-bit CLUT format and the other data stream may be video data in an 8-bit YUV format. The graphics controller may apply chromakeying to generate the merged pixel stream.

Abstract: A chroma keying device is provided for switching between graphics images and video images. An input signal and a reference are compared to provide a switching signal for performing the switching between graphics and video. A switching signal is provided when the input signal color information indicates that the input signal represents a true black image. Thus, switching is triggered upon black in the chroma keying device of a present invention. The black level is determined when each of the red, blue and green inputs of the device receives substantially zero current. A very sensitive comparison is performed between these input lines and a reference voltage in order to detect this condition. In the chroma keying device of the present invention, this sensitive comparison is accomplished using matched diodes within a common integrated circuit.

Abstract: An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.

Abstract: A request arbitration device is provided for prioritizing requests in a data processing system. A series of requests may arrive at the arbitration device at differing arrival times. The requests are accumulated to form a set of requests which is applied to a priority decode without any information on their relative arrival times. The priority device applies a fixed predetermined priority scheme to these requests. Simultaneously with the prioritizing of the first set of requests by the priority decode, a second set of requests may arrive at different arrival times. The requests of this second set of requests are likewise accumulated by the arbitration logic of a present invention. When arbitration of the first set of requests is complete, the second set of requests is then applied to the priority decode, again without any information with respect to their relative arrival times. The second set of requests is prioritized according to the same fixed predetermined priority scheme as the first set.

Abstract: The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.

Abstract: The reprogrammable RAM cartridge of the present invention is adapted for use as a reprogrammable video game. The cartridge uses an optoisolator connected in a circuit between the shield and ground lines to detect the presence of a signal indicating that the cartridge is in a programmer, rather than in a video game unit. While in the programmer, the program stored in the RAM can be changed. However, when removed from the programmer, the cartridge acts like a standard video game cartridge.