Patents by Inventor Lu-Ping Chiang
Lu-Ping Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8440526Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.Type: GrantFiled: September 23, 2011Date of Patent: May 14, 2013Assignee: Winbound Electronics Corp.Inventors: Hsiu-Han Liao, Lu-Ping Chiang
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Publication number: 20130078775Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: WINBOND ELECTRONICS CORP.Inventors: Hsiu-Han Liao, Lu-Ping Chiang
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Publication number: 20130016560Abstract: A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.Type: ApplicationFiled: January 13, 2012Publication date: January 17, 2013Inventors: Masaru YANO, Lu-Ping CHIANG
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Patent number: 8133777Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of gates each having spacers is formed on the substrate. A plurality of openings is formed between the gates in the memory region. A first material layer is formed in the memory region to cover the gates and fill the openings. A barrier layer is formed on the substrate to cover the gates in the periphery region and the first material layer in the memory region. A second material layer is formed on the substrate in the periphery region to cover the barrier layer in the periphery region. The barrier layer covering the first material layer is removed. The first material layer is partially removed to form a plurality of second openings. Each second opening is disposed on a top of the gate in the memory region.Type: GrantFiled: February 15, 2011Date of Patent: March 13, 2012Assignee: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Hsiu-Han Liao
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Patent number: 8124488Abstract: A method of fabricating a memory is provided. A substrate comprising a memory region and a periphery region is provided. A plurality of gates is formed on the substrate and a first spacer is formed on a sidewall of each gate, where a plurality of openings is formed between the gates in the memory region. A first material layer formed on the substrate in the memory region covers the gates in the memory region and fills the openings. A process is performed to the periphery region. The first material layer is partially removed to form a first pattern in each opening respectively. A second material layer formed on the substrate covers the memory region and the periphery region to expose the first patterns. The first patterns are removed to form a plurality of contact openings in the second material layer. The contact plugs are formed in the contact openings.Type: GrantFiled: February 12, 2010Date of Patent: February 28, 2012Assignee: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Hsiu-Han Liao
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Patent number: 8084320Abstract: A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the substrate, each of which includes a control gate and a gate dielectric layer. The control gates are disposed on the substrate, and two first spacers are deployed at both sides of each control gate. The gate dielectric layers are disposed between the control gates and the substrate, respectively. Each of the doped regions is formed in the substrate between two adjacent gate structures. The second spacers are disposed on the sidewalls of the gate structures. The contact plugs are formed between two adjacent second spacers, respectively.Type: GrantFiled: July 13, 2009Date of Patent: December 27, 2011Assignee: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Hsiu-Han Liao
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Publication number: 20110201170Abstract: A method of fabricating a memory is provided. A substrate comprising a memory region and a periphery region is provided. A plurality of gates is formed on the substrate and a first spacer is formed on a sidewall of each gate, where a plurality of openings is formed between the gates in the memory region. A first material layer formed on the substrate in the memory region covers the gates in the memory region and fills the openings. A process is performed to the periphery region. The first material layer is partially removed to form a first pattern in each opening respectively. A second material layer formed on the substrate covers the memory region and the periphery region to expose the first patterns. The first patterns are removed to form a plurality of contact openings in the second material layer. The contact plugs are formed in the contact openings.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Applicant: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Hsiu-Han Liao
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Patent number: 7906396Abstract: In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation structures in a periphery region and the isolation structure in a cell region adjacent to the periphery region. The isolation structures in the cell region not covered by the mask layer are partially removed. Therefore, a first height difference is between surfaces of the isolation structures in the periphery region and a surface of the dielectric layer, and between a surface of the isolation structure in the cell region adjacent to the periphery region and the surface of the dielectric layer. A second height difference smaller than the first height difference is between surfaces of other isolation structures in the cell region and the surface of the dielectric layer.Type: GrantFiled: September 2, 2009Date of Patent: March 15, 2011Assignee: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Hsiu-Han Liao
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Publication number: 20110053338Abstract: In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation structures in a periphery region and the isolation structure in a cell region adjacent to the periphery region. The isolation structures in the cell region not covered by the mask layer are partially removed. Therefore, a first height difference is between surfaces of the isolation structures in the periphery region and a surface of the dielectric layer, and between a surface of the isolation structure in the cell region adjacent to the periphery region and the surface of the dielectric layer. A second height difference smaller than the first height difference is between surfaces of other isolation structures in the cell region and the surface of the dielectric layer.Type: ApplicationFiled: September 2, 2009Publication date: March 3, 2011Applicant: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Hsiu-Han Liao
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Publication number: 20110006356Abstract: A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the substrate, each of which includes a control gate and a gate dielectric layer. The control gates are disposed on the substrate, and two first spacers are deployed at both sides of each control gate. The gate dielectric layers are disposed between the control gates and the substrate, respectively. Each of the doped regions is formed in the substrate between two adjacent gate structures. The second spacers are disposed on the sidewalls of the gate structures. The contact plugs are formed between two adjacent second spacers, respectively.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: Winbond Electonics Corp.Inventors: LU-PING CHIANG, Hsiu-Han Liao
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Patent number: 7385867Abstract: A method of operating a memory device adapted for determining a program/erase state of a memory cell in the memory device. The method includes applying a drain operation voltage to a drain of the memory cell so that the memory cell generates a working voltage. The working voltage is a function of the drain operation voltage. Then, the working voltage to the drain operation voltage is differentiated to obtain a slope of the working voltage to the drain operation voltage. The program/erase state of the memory cell is determined according to the slope.Type: GrantFiled: December 20, 2006Date of Patent: June 10, 2008Assignee: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Po-An Chen
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Publication number: 20080025086Abstract: A method of operating a memory device adapted for determining a program/erase state of a memory cell in the memory device. The method includes applying a drain operation voltage to a drain of the memory cell so that the memory cell generates a working voltage. The working voltage is a function of the drain operation voltage. Then, the working voltage to the drain operation voltage is differentiated to obtain a slope of the working voltage to the drain operation voltage. The program/erase state of the memory cell is determined according to the slope.Type: ApplicationFiled: December 20, 2006Publication date: January 31, 2008Applicant: WINBOND ELECTRONICS CORP.Inventors: LU-PING CHIANG, PO-AN CHEN
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Patent number: 7184336Abstract: A method for evaluating threshold voltage distribution of memory cells. The method comprises connecting all sources and drains of memory cells in a memory array to a fixed voltage; measuring charge pumping current characteristic of a single memory cell versus a first gate voltage and second gate voltage respectively. The total charge pumping current characteristic of a memory array is then measured versus a first gate voltage and second gate voltage respectively. The charge pumping current characteristics of the single memory cell is compared to that of the memory array to obtain a range of threshold voltage distribution.Type: GrantFiled: April 13, 2005Date of Patent: February 27, 2007Assignee: Winbond Electronics Corp.Inventors: Lu-Ping Chiang, Chien-Min Wu, Po-An Chen
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Publication number: 20060039212Abstract: A method for evaluating threshold voltage distribution of memory cells. The method comprises connecting all sources and drains of memory cells in a memory array to a fixed voltage; measuring charge pumping current characteristic of a single memory cell versus a first gate voltage and second gate voltage respectively. The total charge pumping current characteristic of a memory array is then measured versus a first gate voltage and second gate voltage respectively. The charge pumping current characteristics of the single memory cell is compared to that of the memory array to obtain a range of threshold voltage distribution.Type: ApplicationFiled: April 13, 2005Publication date: February 23, 2006Inventors: Lu-Ping chiang, Chien-Min Wu, Po-An Chen