Patents by Inventor Luc Ouellet

Luc Ouellet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6555441
    Abstract: A method is disclosed for aligning structures on first and second opposite sides of a wafer. First one or more transparent islands are formed on the first side of the wafer at an alignment location. The transparent islands have an exposed front side and a rear side embedded in the wafer. At least one alignment mark is formed on the front side of the transparent island. An anisotropic etch is performed through the second side of said the to form an opening substantially reaching the back side of the transparent island. A precise alignment is then carried out on the alignment mark through the opening and the transparent island. In this way a very precise alignment can be carried out on the back side of the wafer for manufacturing MEMS structures.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: April 29, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventor: Luc Ouellet
  • Publication number: 20030070451
    Abstract: A method of making optical quality films is described. A silica film is deposited on a wafer by PECVD (Plasma Enhanced Chemical Vapor Deposition). The deposited film is then subjected to a first heat treatment to reduce optical absorption, wafer warp, and compressive stress. A second film is deposited. This step is then followed by a second heat treatment to reduce optical absorption, wafer warp and tensile stress. The two heat treatments have similar temperature profiles.
    Type: Application
    Filed: October 11, 2001
    Publication date: April 17, 2003
    Inventors: Luc Ouellet, Jonathan Lachance
  • Publication number: 20030068844
    Abstract: A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 10, 2003
    Inventors: Stephane Martel, Yan Riopel, Sebastien Michel, Luc Ouellet
  • Publication number: 20030059556
    Abstract: A method is disclosed for depositing an optical quality silica film on a wafer by PECVD. The flows rates for a raw material gas, an oxidation gas, a carrier gas, and a dopant gas are first set at predetermined levels. The total deposition pressure is set at a predetermined level. The deposited film is then subjected to a post deposition heat treatment at a temperature selected to optimize the mechanical properties without affecting the optical properties. Finally, the observed FTIR characteristics of the deposited film are monitored to produce a film having the desired optical and mechanical properties. This technique permits the production of high quality optical films with reduced stress.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 27, 2003
    Inventors: Luc Ouellet, Jonathan Lachance
  • Patent number: 6537623
    Abstract: An improved high temperature chemical treatment of deposited silica films wherein they are subjected to a reactive ambient comprising hydrogen and oxygen atoms. This method results in better elimination of residual undesirable oscillators so as to provide improved optical quality silica waveguides with reduced optical absorption.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: March 25, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Luc Ouellet, Manuel Grondin
  • Publication number: 20030032299
    Abstract: A method is disclosed for aligning structures on first and second opposite sides of a wafer. First one or more transparent islands are formed on the first side of the wafer at an alignment location. The transparent islands have an exposed front side and a rear side embedded in the wafer. At least one alignment mark is formed on the front side of the transparent island. An anisotropic etch is performed through the second side of said the to form an opening substantially reaching the back side of the transparent island. A precise alignment is then carried out on the alignment mark through the opening and the transparent island. In this way a very precise alignment can be carried out on the back side of the wafer for manufacturing MEMS structures.
    Type: Application
    Filed: August 8, 2001
    Publication date: February 13, 2003
    Inventor: Luc Ouellet
  • Publication number: 20030022505
    Abstract: In a method of fabricating a microstructure for micro-fluidics applications, a mechanically stable support layer is formed over a layer of etchable material. An anisotropic etch is preformed through a mask to form a pattern of holes extending through the support layer into said etchable material. An isotropic etch is performed through each said hole to form a corresponding cavity in the etchable material under each hole and extending under the support layer. A further layer of depositable material is formed over the support layer until portions of the depositable layer overhanging each said hole meet and thereby close the cavity formed under each hole. The invention permits the formation of micro-channels and filters of varying configuration.
    Type: Application
    Filed: July 24, 2001
    Publication date: January 30, 2003
    Inventors: Luc Ouellet, Heather Tyler
  • Publication number: 20020192393
    Abstract: To deposit optical quality films by PECVD (Plasma Enhanced Chemical Vapour Deposition), a six-dimensional space wherein five dimensions thereof correspond to five respective independent variables of which a set of four independent variables relate to the flow-rate of respective gases, a fifth independent variable relates to total pressure, and a six dimension relates to observed FTIR characteristics is first created. Then an optical film is deposited while maintaining three of the set of four independent variables substantially constant as well as the fifth independent variable, and varying a fourth of the set of four independent variables to obtain desired characteristics in the sixth dimension.
    Type: Application
    Filed: May 31, 2001
    Publication date: December 19, 2002
    Inventors: Luc Ouellet, Jonathan Lachance, Manuel Grondin, Stephane Blain
  • Publication number: 20020182342
    Abstract: A method of depositing an optical quality silica film on a substrate is described wherein the film is formed on the substrate by plasma enhanced chemical vapor deposition (PECVD) in the presence of reactive gases while controlling the total pressure of the gases. The as-deposited film is then subjected to a low temperature treatment between 400° to 1200° C. to minimize the presence of contaminant compounds in the film.
    Type: Application
    Filed: April 13, 2001
    Publication date: December 5, 2002
    Inventors: Luc Ouellet, Manuel Grondin, Jonathan Lachance, Stephane Blain
  • Publication number: 20020160561
    Abstract: In a method of fabricating a microstructure for microfluidics applications, a first layer of etchable material is formed on a suitable substrate. A mechanically stable support layer is formed over the etchable material. A mask is applied over the support to expose at least one opening in the mask. An anistropic etch is then performed through the opening to create a bore extending through the support layer to said layer of etchable material. After performing an isotropic etch through the bore to form a microchannel in the etchable material extending under the support layer, a further layer is deposited over the support layer until overhanging portions meet and thereby close the microchannel formed under the opening.
    Type: Application
    Filed: April 27, 2001
    Publication date: October 31, 2002
    Inventors: Luc Ouellet, Heather Tyler
  • Publication number: 20020071914
    Abstract: An improved high temperature chemical treatment of deposited silica films wherein they are subjected to a reactive ambient comprising hydrogen and oxygen atoms. This method results in better elimination of residual undesirable oscillators so as to provide improved optical quality silica waveguides with reduced optical absorption.
    Type: Application
    Filed: March 7, 2001
    Publication date: June 13, 2002
    Inventors: Luc Ouellet, Manuel Grondin
  • Publication number: 20020064359
    Abstract: A method is disclosed for making a device having one or more deposited layers and subject to a post deposition high temperature anneal. Opposing films having similar mechanical properties are deposited on the front and back faces of a wafer, which is subsequently subjected a high temperature anneal. The opposing films tend to cancel out stress-induced warping of the wafer during the subsequent anneal.
    Type: Application
    Filed: March 7, 2001
    Publication date: May 30, 2002
    Inventors: Luc Ouellet, Annie Dallaire
  • Patent number: 6348738
    Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another.
    Type: Grant
    Filed: August 11, 1999
    Date of Patent: February 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jean Dery, Frank D. Egitto, Luis J. Matienzo, Charles Ouellet, Luc Ouellet, David L. Questad, William J. Rudik, Son K. Tran
  • Patent number: 6306683
    Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treat with the plasma before they are joined to one another.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: October 23, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jean Dery, Frank D. Egitto, Luis J. Matienzo, Charles Ouellet, Luc Ouellet, David L. Questad, William J. Rudik, Son K. Tran
  • Patent number: 6268620
    Abstract: A method of making a semiconductor device, comprises the steps of providing an insulating layer, forming a series of holes in the insulating layer, depositing a first layer of a metal, or a compound thereof, on the insulating layer such and in the holes, forming a dielectric layer on the first layer, the dielectric consisting of a compound of the metal, and forming a second layer of the metal, or a compound thereof, on the dielectric layer. The first, second and dielectric layers form a conformal capacitive sandwich structure extending into the holes.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: July 31, 2001
    Assignee: Mitel Corporation
    Inventors: Luc Ouellet, Yves Tremblay
  • Patent number: 6133060
    Abstract: A semiconductor device includes at least one active region. A thick dielectric film with an opaque layer embedded therein is deposited over the light sensitive active regions to provide protection from incident light without detrimentally affecting the optical properties of an uppermost optically active layer. An active layer is deposited over the thick dielectric film.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: October 17, 2000
    Assignee: Mitel Corporation
    Inventors: Ted Darwall, Luc Ouellet
  • Patent number: 6127266
    Abstract: A method of manufacturing a semiconductor device which includes an interface between a metal layer and a barrier layer of a nitride of a refractory metal, comprising the steps of depositing the barrier layer onto a wafer at high temperature; subjecting the barrier layer to a mixture of oxygen or an oxygen-containing gas and an inert gas in the presence of a plasma at low pressure and for a time sufficient to oxidize the surface of the barrier layer; removing the oxygen-containing gas; and depositing the metal layer onto the oxidized surface without subjecting said wafer to an air break. The method permits high throughput to be achieved at low cost.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: October 3, 2000
    Assignee: Mitel Corporation
    Inventors: Luc Ouellet, Yves Tremblay, Luc Gendron
  • Patent number: 6083805
    Abstract: A method of forming capacitors in a semiconductor device, involves providing a first insulating layer, providing a first mask with an array of apertures over the insulating layer, and etching an array of holes in the first insulating layer through said apertures in said first mask. A first electrode layer extending into the holes is formed over the first insulating layer. A second dielectric layer extends into the holes on said first electrode layer. A second electrode layer extends into the holes on the dielectric layer. The capacitors are patterned with a second mask. The capacitors can be subsequently connected into the circuit in a sequence of processing steps that only involve the addition two extra masks beyond those conventionally employed in integrated circuit manufacture.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: July 4, 2000
    Assignee: Mitel Corporation
    Inventors: Luc Ouellet, Stephane Blain
  • Patent number: 6074895
    Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the a surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O.sub.2 plasma or a microwave-generated Ar and N.sub.2 O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: June 13, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jean Dery, Frank D. Egitto, Luis J. Matienzo, Charles Ouellet, Luc Ouellet, David L. Questad, William J. Rudik, Son K. Tran
  • Patent number: 6074946
    Abstract: A method of fabricating a semiconductor device includes etching holes through at least one deposited layer to an underlying structure. A hard mask is deposited on an upper surface of a device to be etched, the mask is patterned with the aid of a photoresist, and holes are etched in the hard mask. After removal of the photoresist, contact or via holes are etched through the patterned hard mask in the deposited layer(s) to reach the underlying structure.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: June 13, 2000
    Assignee: Mitel Corporation
    Inventors: Luc Ouellet, Abdellah Azelmad