Abstract: A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells.

Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

Abstract: Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by a plurality of comparators is connected to the high-voltage output and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output and a plurality of reference voltages, one for each comparator. The charge-pump stages are grouped into sets of stages, and the stages belonging to a same set receive a same enabling signal; thus, as many comparators as there are sets of stages are present.

Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract: A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.

Abstract: A method of electrically programming a memory cell includes: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the memory cell; and repeating the acts of applying and verifying until the reaching of a target programming state by the memory cell is assessed. After the reaching of a target programming state by the memory cells is assessed, at least one further electrical programming pulse is applied thereto, and the memory cell is verified at least one more time after applying the further programming pulse. In case, as a result of said further verifying, the reaching of the target programming state by the memory cell is not assessed, the method provides for applying a still further programming pulse to the memory cell.

Abstract: An embodiment of an electronic apparatus is provided. The electronic apparatus includes a supplying block for supplying a plurality of operative voltages, one or more operative circuits and a distribution bus for distributing at least part of the operative voltages to each operative circuit. Each operative circuit includes a set of devices for generating a set of output voltages from a set of input ones of the distributed operative voltages. The input and output voltages span an effective range. Each device is capable of sustaining at most a safe voltage between each pair of terminals thereof not higher than the effective range. The devices are controlled by a set of auxiliary ones of the distributed operative voltages spanning an auxiliary range within the effective range, so that a difference between the voltage applied to each pair of terminals thereof is not higher than the safe voltage.

Abstract: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

Abstract: A memory device is provided. The memory device includes a matrix of memory cells adapted to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction; a page buffer adapted to interface the matrix with a downstream circuitry, the page buffer comprising a plurality of read/program units. Each read/program unit is associated with at least one bit line. The memory device further includes at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction. Each group comprises at least one signal track shared by the at least two read/program units of the group.

Abstract: A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells. The read/program unit is adapted to at least temporarily store data bits read from or to be written into selected memory cells and comprises programming state change enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential.

Abstract: A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.

Abstract: A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.

Abstract: The evaluation time or the difference between the read charge voltage and the read discrimination voltage of the programmed or erased state of a cell of a NAND memory array is set for the individual memory device. This is done in such a way that at least partially compensates the generally large spread of parasitic capacitance values of the array bitlines in the mass production fabrication process of the NAND memory array.

Abstract: A voltage regulator integrated in a chip of semiconductor material is provided.

Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell.

Abstract: An embodiment of an electronic apparatus is provided. The electronic apparatus includes a supplying block for supplying a plurality of operative voltages, one or more operative circuits and a distribution bus for distributing at least part of the operative voltages to each operative circuit. Each operative circuit includes a set of devices for generating a set of output voltages from a set of input ones of the distributed operative voltages. The input and output voltages span an effective range. Each device is capable of sustaining at most a safe voltage between each pair of terminals thereof not higher than the effective range. The devices are controlled by a set of auxiliary ones of the distributed operative voltages spanning an auxiliary range within the effective range, so that a difference between the voltage applied to each pair of terminals thereof is not higher than the safe voltage.

Abstract: A method of electrically programming a memory cell includes: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the memory cell; and repeating the acts of applying and verifying until the reaching of a target programming state by the memory cell is assessed. After the reaching of a target programming state by the memory cells is assessed, at least one further electrical programming pulse is applied thereto, and the memory cell is verified at least one more time after applying the further programming pulse. In case, as a result of said further verifying, the reaching of the target programming state by the memory cell is not assessed, the method provides for applying a still further programming pulse to the memory cell.

Abstract: A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.