Patents by Inventor Luigi Pilolli
Luigi Pilolli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200343880Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.Type: ApplicationFiled: April 23, 2019Publication date: October 29, 2020Inventors: Ali Feiz Zarrin Ghalam, Luigi Pilolli, Myung Gyoo Won
-
Patent number: 10819296Abstract: Apparatus useful for receiving or transmitting voltage signals might include a current generator having first and second inputs and configured to generate a current flow between first and second outputs responsive to a voltage difference between its first and second inputs. The apparatus might further include a feedback amplifier having a first input connected to the first output of the current generator, a second input connected to the second output of the current generator, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.Type: GrantFiled: March 22, 2019Date of Patent: October 27, 2020Assignee: Micron Technology, Inc.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli
-
Publication number: 20200304086Abstract: Apparatus useful for receiving or transmitting voltage signals might include a current generator having first and second inputs and configured to generate a current flow between first and second outputs responsive to a voltage difference between its first and second inputs. The apparatus might further include a feedback amplifier having a first input connected to the first output of the current generator, a second input connected to the second output of the current generator, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.Type: ApplicationFiled: March 22, 2019Publication date: September 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Agatino Massimo Maccarrone, Luigi Pilolli
-
Publication number: 20200176059Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Luigi Pilolli, Agatino Massimo Maccarrone, Hoon Choi, Qiang Tang, Ali Feiz Zarrin Ghalam
-
Patent number: 10658041Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.Type: GrantFiled: November 30, 2018Date of Patent: May 19, 2020Assignee: Micron Technology, Inc.Inventors: Luigi Pilolli, Agatino Massimo Maccarrone, Hoon Choi, Qiang Tang, Ali Feiz Zarrin Ghalam
-
Publication number: 20200133540Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Luigi Pilolli, Ali Feiz Zarrin Ghalam, Guan Wang, Qiang Tang
-
Patent number: 10446258Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: GrantFiled: October 2, 2017Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
-
Patent number: 10359944Abstract: Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. The analog controller is configured to determine, in response to the indication, what analog voltages should be generated by the analog voltage generation circuit for the apparatus to perform the interpreted command. The data cache controller is configured to determine, in response to the indication, whether the data cache should be configured to accept data from the memory array or to provide data to the memory array for the apparatus to perform the interpreted command.Type: GrantFiled: August 30, 2017Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Luigi Pilolli
-
Publication number: 20190004938Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Umberto Siciliani, Giulio Giuseppe Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano, Luigi Pilolli, Giovanni Santin, Michele Incarnati
-
Patent number: 10170167Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.Type: GrantFiled: May 23, 2016Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: Mauro Castelli, Luca De Santis, Luigi Pilolli, Maria Luisa Gallese
-
Patent number: 9940193Abstract: The present disclosure is related to chunk definition for partial-page read. A number of methods can include setting a chunk size for a partial-page read of a page of memory cells. A start address of the partial-page read and chunk size can define a chunk of the page of memory cells. Some method can include enabling only those of a plurality of sense amplifiers associated with the page of memory cells that correspond to the chunk to perform the partial-page read.Type: GrantFiled: June 6, 2014Date of Patent: April 10, 2018Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Luigi Pilolli
-
Publication number: 20180047460Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: ApplicationFiled: October 2, 2017Publication date: February 15, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
-
Publication number: 20170364268Abstract: Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. The analog controller is configured to determine, in response to the indication, what analog voltages should be generated by the analog voltage generation circuit for the apparatus to perform the interpreted command. The data cache controller is configured to determine, in response to the indication, whether the data cache should be configured to accept data from the memory array or to provide data to the memory array for the apparatus to perform the interpreted command.Type: ApplicationFiled: August 30, 2017Publication date: December 21, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Luigi Pilolli
-
Patent number: 9779839Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data.Type: GrantFiled: November 13, 2015Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
-
Patent number: 9772779Abstract: Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.Type: GrantFiled: April 14, 2016Date of Patent: September 26, 2017Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Luigi Pilolli
-
Publication number: 20160267953Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.Type: ApplicationFiled: May 23, 2016Publication date: September 15, 2016Inventors: Mauro Castelli, Luca De Santis, Luigi Pilolli, Maria Luisa Gallese
-
Publication number: 20160231930Abstract: Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Luigi Pilolli
-
Patent number: 9349423Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.Type: GrantFiled: September 3, 2014Date of Patent: May 24, 2016Assignee: Micron Technology, Inc.Inventors: Mauro Castelli, Luca De Santis, Luigi Pilolli, Maria Luisa Gallese
-
Patent number: 9317459Abstract: A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.Type: GrantFiled: January 26, 2012Date of Patent: April 19, 2016Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Luigi Pilolli
-
Publication number: 20160071619Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: ApplicationFiled: November 13, 2015Publication date: March 10, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli