Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: In some embodiments, a shared IO device includes a plurality of packet filters associated with a plurality of virtual systems sharing the shared I/O device and a plurality of filter receive queues assigned to the plurality of packet filters. A processor is responsive to a receive packet to determine if the receive packet matches one of the plurality of packet filters and the processor, upon determining that there is a matched packet filter, is adapted to place the receive packet in the filter receive queue assigned to the matched packet filter.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

Abstract: Described are a device and system to transmit 8B/10B code groups including Ethernet data frames in a device-to-device interconnection. Control messages may be interleaved among the 8B/10B code groups for transmission to a destination device.

Abstract: Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: A system and method to implement a dual speed network interface. A first code is transmitted from an initiator unit to a follower unit on a first output datapath (“OUT_DP”) of multiple OUT_DPs coupling the initiator unit to the follower unit. The first code is transmitted to initiate a speed change of a link to a physical medium for communicating data. The first code is transmitted at a first datapath speed. A second code is received on a first input datapath (“IN_DP”) of multiple IN_DPs coupling the follower unit to the initiator unit. The second code indicates to the initiator unit that the follower unit received the first code. The first OUT_DP is then placed into an idle state in response to receiving the second code. Subsequently, the first OUT_DP is enabled after the idle state at a second datapath speed different from the first datapath speed.

Abstract: In some embodiments, a shared IO device includes a plurality of packet filters associated with a plurality of virtual systems sharing the shared I/O device and a plurality of filter receive queues assigned to the plurality of packet filters. A processor is responsive to a receive packet to determine if the receive packet matches one of the plurality of packet filters and the processor, upon determining that there is a matched packet filter, is adapted to place the receive packet in the filter receive queue assigned to the matched packet filter.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.

Abstract: In one aspect, a shared transport layer frame information structure (FIS) generation logic may generate FISes for each of a plurality of SATA ports. In a further aspect, a port addressing logic, in communication with the shared transport layer FIS generation logic, may select one of the SATA ports for each of the FISes.

Abstract: A method and apparatus for transfer of power state data between network components. An embodiment of a method includes determining a command for a computer system, the computer system including a first network component and a second network component. The first network component and the second network component are linked by an interface. The method further includes inserting a message regarding the power state change in a data frame and transferring the data frame from the first network component to the second component via the interface, the data frame being transferred in a period between data packets.

Abstract: A system and method to implement a dual speed network interface. A first code is transmitted from an initiator unit to a follower unit on a first output datapath (“OUT_DP”) of multiple OUT_DPs coupling the initiator unit to the follower unit. The first code is transmitted to initiate a speed change of a link to a physical medium for communicating data. The first code is transmitted at a first datapath speed. A second code is received on a first input datapath (“IN_DP”) of multiple IN_DPs coupling the follower unit to the initiator unit. The second code indicates to the initiator unit that the follower unit received the first code. The first OUT_DP is then placed into an idle state in response to receiving the second code. Subsequently, the first OUT_DP is enabled after the idle state at a second datapath speed different from the first datapath speed.

Abstract: An apparatus, system, and method to provide a dual speed bi-directional link between a media access control (“MAC”) unit and a physical (“PHY”) unit. The MAC unit controls access to a physical medium and the PHY unit couples to the physical medium. A bi-directional link couples first transmit data paths (“TXDPs”) and first receive data paths (“RXDPs”) of the MAC unit to second TXDPs and second RXDPs of the PHY unit. The MAC and PHY units configured to route data along all of the first and second TXDPs and RXDPs during fast speed operation and to route the data along one of the first and second TXDPs and one of the first and second RXDPs during the slow speed operation.

Abstract: A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to-recover the bitstream.

Abstract: Described are a device and system to transmit 8B/10B code groups including Ethernet data frames in a device-to-device interconnection. Control messages may be interleaved among the 8B/10B code groups for transmission to a destination device.