Abstract: A method for assembling at least one stacked substrate package, each stacked substrate package includes binding a laminated base substrate, configured to route interconnections between circuitry on a first surface of the laminated base substrate and circuitry on a second surface of the laminated base substrate, to a surface of a rigid carrier to prevent warping of the laminated base substrate. Each base substrate is coupled to at least one dielectric build-up substrate, which is configured to route integrated interconnections between a top surface and a bottom surface of the dielectric build-up substrate, to the laminated base substrate. At least one integrated circuit die is coupled to the at least one dielectric build-up substrate, and then the carrier is released from the laminated base substrate to form an assembled stacked substrate package. Also, multiple stacked substrate packages may be assembled in parallel on one carrier.

Abstract: An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.

Abstract: Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.

Abstract: Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.

Abstract: A stacked semiconductor device is provided, which includes a first die, a second die and a heat dissipating layer. The first die has a pre-determined size. The second die is bonded to the first die using a dielectric material, wherein the second die is smaller than the first die. The heat dissipating layer is surrounding the second die, wherein the heat dissipating layer has an outer dimension that is equal to the size of the first die.

Abstract: A stacked semiconductor device is provided, which includes a first die, a second die and a heat dissipating layer. The first die has a pre-determined size. The second die is bonded to the first die using a dielectric material, wherein the second die is smaller than the first die. The heat dissipating layer is surrounding the second die, wherein the heat dissipating layer has an outer dimension that is equal to the size of the first die.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.

Abstract: A product disclosed herein includes an RF filter die including an RF filter, a front side and a plurality of conductive bond pads conductively coupled to at least a portion of the RF filter, wherein at least a portion of the conductive bond pads is exposed on the front side of the RF filter die. The product also includes a TSV (Through-Substrate-Via) die that includes a plurality of conductive TSV contacts positioned on a back side of the TSV die and at least one conductive TSV (Through-Substrate-Via) structure that is conductively coupled to at least one of the plurality of conductive TSV contacts, wherein the back side of the TSV die is bonded to the front side of the RF filter such that the conductive bond pads on the RF filter die are conductively coupled to corresponding conductive TSV contacts positioned on the back side of the TSV die.

Abstract: A product disclosed herein includes an RF filter die including an RF filter, a front side and a plurality of conductive bond pads conductively coupled to at least a portion of the RF filter, wherein at least a portion of the conductive bond pads is exposed on the front side of the RF filter die. The product also includes a TSV (Through-Substrate-Via) die that includes a plurality of conductive TSV contacts positioned on a back side of the TSV die and at least one conductive TSV (Through-Substrate-Via) structure that is conductively coupled to at least one of the plurality of conductive TSV contacts, wherein the back side of the TSV die is bonded to the front side of the RF filter such that the conductive bond pads on the RF filter die are conductively coupled to corresponding conductive TSV contacts positioned on the back side of the TSV die.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.

Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.

Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.

Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.

Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

Abstract: In one aspect, the present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) substrate composed of an active layer, a substrate and a buried insulating layer which is positioned on an upper surface of the substrate and below a lower surface of the active layer. At least one gate electrode having a channel region below is positioned above an upper surface of the active layer and at least one vertical connection element extends between the upper surface of the substrate and an opposite lower surface of the substrate below the at least one gate electrode. The at least one vertical connection element serves for back-biasing FETs with back-bias contacts at the rear side of the wafer.

Abstract: Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.

Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.