Abstract: Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed.

Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

Abstract: A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.

Abstract: This document discusses, among other things, a conductive frame, a silicon die coupled to the conductive frame, the silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a silicon die port extending through the silicon die to the vibratory diaphragm, with a silicon die terminal in electrical communication with the conductive frame and an insulator affixed to the conductive frame and the silicon die, with the insulator extending through interstices in the conductive frame to a conductive frame bottom of the conductive frame, and around an exterior of the silicon die to the silicon die top, with the insulator physically affixed to the silicon die and to the conductive frame, with the silicon die port exposed and with a conductive frame terminal disposed at the conductive frame bottom in electrical communication with the silicon die terminal.

Abstract: An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings.

Abstract: This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions.

Abstract: Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure.

Abstract: Annular reinforcement structures that can be used in wafer level chip scale packages (WLCSP) are described. The WLCSP comprises a substrate with an IC device and a bond pad connected to the IC device, a passivation layer protecting an outer portion of the bond pad, an annular ring structure formed on an inner portion of the bond pad, an under bump metal (UBM) layer covering the annular ring structure, and a solder ball attached to the UBM layer. The annular ring structure contains a substantially planar top with vertical or non-vertical sidewalls that slope down to the inner portion of the bond pad. The annular ring structure can slow the solder crack propagation in the solder ball and therefore increase the solder joint reliability in the WLCSP. As well, the annular ring structure can increase the surface area for solder attachment to the UBM layer, improving overall ball shear strength are described. Other embodiments are described.

Abstract: This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions.

Abstract: This document discusses, among other things, a conductive frame, a silicon die coupled to the conductive frame, the silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a silicon die port extending through the silicon die to the vibratory diaphragm, with a silicon die terminal in electrical communication with the conductive frame and an insulator affixed to the conductive frame and the silicon die, with the insulator extending through interstices in the conductive frame to a conductive frame bottom of the conductive frame, and around an exterior of the silicon die to the silicon die top, with the insulator physically affixed to the silicon die and to the conductive frame, with the silicon die port exposed and with a conductive frame terminal disposed at the conductive frame bottom in electrical communication with the silicon die terminal.

Abstract: An imager device is disclosed which includes at least one photosensitive element positioned on a front surface of a substrate and a conductive structure extending at least partially through an opening defined in the substrate to conductively couple to an electrical contact or bond pad on the front surface. An insulating material of a conductive laminate film and/or a mold compound material is positioned within the opening between at least a portion of the conductive structure and the substrate. Also disclosed is a device that comprises a substrate and a plurality of openings in the substrate, wherein each of the openings is adapted to be positioned above an imager device when the substrate is positioned above and secured to an imager substrate. A method of forming an imager device is also disclosed.

Abstract: An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings.

Abstract: An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings.

Abstract: In one form a stackable electrical device package has a first plurality of traces, the electrical device bonded to at least some of the first plurality of traces, a second plurality of vertical posts attached to the first plurality of traces, and encapsulation material enclosing the electrical device and sides of the first plurality of traces and the second plurality of vertical posts such that bottoms of the first plurality of traces are exposed on the bottom of the semiconductor package, and tops of the vertical posts are exposed on the top of the semiconductor package.

Abstract: An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings.

Abstract: A module that provides EMI shielding for imager devices is disclosed which includes a die comprising an imager device and a plurality of contact pads, a stack positioned above the imager device, the stack comprising at least one lens, a conductive layer positioned above the stack, the conductive layer comprising at least one light opening, and a plurality of wire bonds, each of which conductively couples the conductive layer to one of the contact pads on the die. A method of providing EMI shielding for an imager module is also disclosed which includes conductively coupling a conductive layer of the module to a plurality of contact pads on an imager die and forming an encapsulant material that encapsulates at least the plurality of wire bonds, the conductive layer and the contact pads.

Abstract: A module that provides EMI shielding for imager devices is disclosed which includes a die comprising an imager device and a plurality of contact pads, a stack positioned above the imager device, the stack comprising at least one lens, a conductive layer positioned above the stack, the conductive layer comprising at least one light opening, and a plurality of wire bonds, each of which conductively couples the conductive layer to one of the contact pads on the die. A method of providing EMI shielding for an imager module is also disclosed which includes conductively coupling a conductive layer of the module to a plurality of contact pads on an imager die and forming an encapsulant material that encapsulates at least the plurality of wire bonds, the conductive layer and the contact pads.

Abstract: An imager device is disclosed which includes at least one photosensitive element positioned on a front surface of a substrate and a conductive structure extending at least partially through an opening defined in the substrate to conductively couple to an electrical contact or bond pad on the first surface. An insulating material of a conductive laminate film and/or a mold compound material is positioned within the opening between at least a portion of the conductive structure and the substrate. Also disclosed is a device that comprises a substrate and a plurality of openings in the substrate, wherein each of the openings is adapted to be positioned above an imager device when the substrate is positioned above and secured to an imager substrate. A method of forming an imager device is also disclosed.