Patents by Inventor Lyle D. Breiner
Lyle D. Breiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7112544Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: GrantFiled: May 13, 2004Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Patent number: 7056806Abstract: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.Type: GrantFiled: September 17, 2003Date of Patent: June 6, 2006Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Trung T. Doan, Ronald A. Weimer, Kevin L. Beaman, Lyle D. Breiner, Lingyi A. Zheng, Er-Xuan Ping, Demetrius Sarigiannis, David J. Kubista
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Patent number: 6916723Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.Type: GrantFiled: April 25, 2003Date of Patent: July 12, 2005Assignee: Micron Technology, Inc.Inventors: Shenlin Chen, Trung Tri Doan, Guy T. Blalock, Lyle D. Breiner, Er-Xuan Ping
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Patent number: 6887755Abstract: The invention encompasses a method of forming a rugged silicone-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40° C. higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.Type: GrantFiled: September 5, 2003Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Guy T. Blalock, Lyle D. Breiner
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Patent number: 6881636Abstract: The invention includes methods of forming deuterated silicon nitride-containing materials from at least one deuterated nitrogen compound in combination with one or more silicon-containing compounds that do not contain hydrogen isotopes. Suitable deuterated nitrogen compounds can comprise, for example, NH2D, NHD2 and ND3. Suitable silicon-containing compounds include, for example, SiCl4 and Si2Cl6. Deuterated silicon nitride-containing materials of the present invention can be incorporated into, for example, transistor devices. The transistor devices can be utilized in DRAM cells, which in turn can be utilized in electronic systems.Type: GrantFiled: July 3, 2003Date of Patent: April 19, 2005Assignee: Micron Technology, Inc.Inventors: Ronald A. Weimer, Lyle D. Breiner
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Patent number: 6835674Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: GrantFiled: April 30, 2004Date of Patent: December 28, 2004Assignee: Micron Technology, Inc.Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20040235302Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: May 13, 2004Publication date: November 25, 2004Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20040212048Abstract: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.Type: ApplicationFiled: April 25, 2003Publication date: October 28, 2004Inventors: Shenlin Chen, Trung Tri Doan, Guy T. Blalock, Lyle D. Breiner, Er-Xuan Ping
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Publication number: 20040203232Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: April 30, 2004Publication date: October 14, 2004Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20030186515Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: March 13, 2002Publication date: October 2, 2003Inventors: Trung Tri Dean, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20030176061Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: January 22, 2003Publication date: September 18, 2003Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20030176060Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: January 22, 2003Publication date: September 18, 2003Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20030176062Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: January 22, 2003Publication date: September 18, 2003Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20030176057Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: January 22, 2003Publication date: September 18, 2003Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Publication number: 20030176047Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.Type: ApplicationFiled: January 22, 2003Publication date: September 18, 2003Inventors: Trung Tri Doan, Lyle D. Breiner, Er-Xuan Ping, Lingyi A. Zheng
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Patent number: 6388284Abstract: Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.Type: GrantFiled: January 3, 2001Date of Patent: May 14, 2002Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Lyle D. Breiner, Philip J. Ireland, Trung Tri Doan, Gurtej S. Sandhu, Sujit Sharan
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Patent number: 6291289Abstract: Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereove. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.Type: GrantFiled: June 25, 1999Date of Patent: September 18, 2001Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Lyle D. Breiner, Philip J. Ireland, Trung Tri Doan, Gurtej S. Sandhu, Sujit Sharan
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Publication number: 20010012656Abstract: Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.Type: ApplicationFiled: June 25, 1999Publication date: August 9, 2001Inventors: HOWARD E. RHODES, LYLE D. BREINER, PHILIP J. IRELAND, TRUNG TRI DOAN, GURTEJ S. SANDHU, SUJIT SHARAN
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Publication number: 20010001210Abstract: Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.Type: ApplicationFiled: January 3, 2001Publication date: May 17, 2001Inventors: Howard E. Rhodes, Lyle D. Breiner, Philip J. Ireland, Trung Tri Doan, Gurtej S. Sandhu, Sujit Sharan
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Patent number: 6121081Abstract: An embodiment of the present invention develops a process for forming Hemi-Spherical Grained silicon by the steps of: forming amorphous silicon from a gas source comprising at least one of dichlorosilane, disilane or trisilane, wherein the amorphous silicon comprising at least one impurity doped amorphous portion, the amorphous silicon is deposited at a deposition temperature no greater than 525.degree. C.; and annealing the amorphous silicon for a sufficient amount of time and at an elevated annealing temperature, thereby transforming the amorphous silicon into the Hemi-Spherical Grained silicon.Type: GrantFiled: November 16, 1998Date of Patent: September 19, 2000Assignee: Micron Technology, Inc.Inventors: Randhir P. S. Thakur, Lyle D. Breiner