Patents by Inventor Mahalingam Venkatesan

Mahalingam Venkatesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5695819
    Abstract: A thermal decomposition CVD method is provided for forming a polysilicon layer over a stepped surface on a semiconductor wafer. The method includes introducing a continuous flow of silicon precursor gases into a vacuum chamber, and adjusting the flow rates and concentrations of the precursor gases, adjusting the temperature and adjusting the pressure within the vacuum chamber so as to control the growth rate of the polysilicon layer on the substrate to between about 500 angstroms/minute and about 2000 angstroms/minute. In a preferred embodiment of the invention, the growth rate of the polysilicon layer is controlled by adjusting the precursor gas flow rates, the temperature and the pressure to between about 1000 angstroms/minute and about 1500 angstroms/minute with the result that the average step coverage of the polysilicon layer is greater than about 95 percent.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: December 9, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, Mahalingam Venkatesan
  • Patent number: 5645646
    Abstract: An apparatus for depositing a material on a wafer includes a susceptor plate mounted in a deposition chamber. The chamber has a gas inlet and a gas exhaust. Means are provided for heating the susceptor plate. The susceptor plate has a plurality of support posts projecting from its top surface. The support posts are arranged to support a wafer thereon with the back surface of the wafer being spaced from the surface of the susceptor plate. The support posts are of a length so that the wafer is spaced from the susceptor plate a distance sufficient to allow deposition gas to flow and/or diffuse between the wafer and the susceptor plate, but still allow heat transfer from the susceptor plate to the wafer mainly by conduction. The susceptor plate is also provided with means, such as retaining pins or a recess, to prevent lateral movement of a wafer seated on the support posts.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: July 8, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, Mahalingam Venkatesan, Roger N. Anderson
  • Patent number: 5599397
    Abstract: The present disclosure is directed to an apparatus for depositing a layer of a material on a wafer. The apparatus includes a deposition chamber having an upper dome, a lower dome and a side wall between the upper and lower domes. A susceptor plate is in and extends across the deposition chamber to divide the deposition chamber into an upper portion above the susceptor plate and a lower portion below the susceptor plate. A gas inlet manifold is in the side wall. The manifold has three inlet ports. One of the ports is connected by passages which open into the lower portion of the deposition chamber. The other two ports are connected by passages which open into the upper portion of the deposition chamber. A gas supply system is connected to the inlet ports so as to provide the same gases into the lower portion of the deposition chamber as well as into the upper portion of the deposition chamber.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: February 4, 1997
    Assignee: Applied Materials Inc.
    Inventors: Roger N. Anderson, H. Peter W. Hey, Israel Beinglass, Mahalingam Venkatesan
  • Patent number: 5576059
    Abstract: A barrier to prevent reactant gases from reaching the surfaces of a susceptor support for a substrate upon which polysilicon films are to be deposited provides improved uniformity of the depositing film across the substrate, and prevents substrate-to-substrate variations during sequential depositions. A suitable barrier includes a preheat ring extension that mates with an extension of the susceptor support.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 19, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, Mahalingam Venkatesan, Christian M. Gronet
  • Patent number: 5551982
    Abstract: The present disclosure is directed to an apparatus for depositing a layer of a material on a wafer. The apparatus includes a deposition chamber having an upper dome, a lower dome and a side wall between the upper and lower domes. A susceptor plate is in and extends across the deposition chamber to divide the deposition chamber into an upper portion above the susceptor plate and a lower portion below the susceptor plate. A gas inlet manifold is in the side wall. The manifold has three inlet ports. One of the ports is connected by passages which open into the lower portion of the deposition chamber. The other two ports are connected by passages which open into the upper portion of the deposition chamber. A gas supply system is connected to the inlet ports so as to provide the same gases into the lower portion of the deposition chamber as well as into the upper portion of the deposition chamber.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: September 3, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Roger N. Anderson, H. Peter W. Hey, Israel Beinglass, Mahalingam Venkatesan
  • Patent number: 5112764
    Abstract: A method of manufacturing a thin film transistor having a low leakage current including depositing a layer of silicon oxide on a semiconductor substrate or on a layer of silicon nitrate deposited on a glass substrate, depositing a polysilicon layer, at a temperature of 520.degree.-570.degree. C., on the silicon oxide layer, annealing this polysilicon layer in a nitrogen atmosphere at a temperature of less than 650.degree. C., forming islands in this polysilicon layer, forming a gate oxide layer on one of the islands by oxidizing the island under high pressure at a temperature below 650.degree. C., forming a gate from a heavily doped polysilicon layer deposited on the gate oxide layer, forming lightly doped source and drain areas laterally adjacent to the gate, providing a thin layer of silicon oxide on the gate and the source and drain access, heavily doping areas of the first silicon layer adjacent to the source and drain areas, annealing the source and drain areas at a temperature below 650.degree. C.
    Type: Grant
    Filed: September 4, 1990
    Date of Patent: May 12, 1992
    Assignee: North American Philips Corporation
    Inventors: Udayanath Mitra, Mahalingam Venkatesan