Patents by Inventor Mahesh Wagh
Mahesh Wagh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210232520Abstract: In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Inventors: Swadesh Choudhary, Mahesh Wagh, Debendra Das Sharma
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Patent number: 11061761Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: GrantFiled: January 31, 2020Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Patent number: 11003610Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.Type: GrantFiled: January 31, 2020Date of Patent: May 11, 2021Assignee: Intel CorporationInventors: Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobel Li, Robert G. Blankenship, Robert J. Safranek
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Publication number: 20210112132Abstract: In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: NITISH PALIWAL, PEEYUSH PUROHIT, SWADESH CHOUDHARY, MANJULA PEDDIREDDY, MAHESH NATU, MAHESH WAGH
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Publication number: 20210109300Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.Type: ApplicationFiled: November 18, 2020Publication date: April 15, 2021Applicant: INTEL CORPORATIONInventors: MAHESH WAGH, MARK S. MYERS, STEPHEN R. VAN DOREN, DIMITRIOS ZIAKAS, BASSAM N. COURY
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Publication number: 20210097015Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Publication number: 20210013999Abstract: Systems and devices can include protocol stack circuitry to perform certain methods, including receiving a flow control unit (flit) header and a transaction layer packet (TLP) payload, the TLP payload comprising a first portion and a second portion, determining that the flit header is free from errors, forwarding the flit header and the first portion of the TLP payload to a link partner based on the flit header being free from errors, identifying that the flit contains an error from the second portion of the TLP payload, and sending a data link layer packet (DLLP) to the link partner to indicate the error in the TLP payload.Type: ApplicationFiled: September 24, 2020Publication date: January 14, 2021Applicant: Intel CorporationInventors: Swadesh Choudhary, Debendra Das Sharma, Mahesh Wagh
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Patent number: 10884195Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.Type: GrantFiled: December 31, 2016Date of Patent: January 5, 2021Assignee: INTEL CORPORATIONInventors: Mahesh Wagh, Mark S. Myers, Stephen R. Van Doren, Dimitrios Ziakas, Bassam Coury
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Publication number: 20200409899Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: ApplicationFiled: September 9, 2020Publication date: December 31, 2020Applicant: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20200409896Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: June 5, 2020Publication date: December 31, 2020Applicant: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Publication number: 20200394150Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Applicant: Intel CorporationInventors: Narasimha Lanka, Swadesh Choudhary, Mahesh Wagh, Lakshmipriya Seshan
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Patent number: 10860515Abstract: Herein is disclosed an integrated input/output (“I/O”) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.Type: GrantFiled: June 21, 2018Date of Patent: December 8, 2020Assignee: INTEL CORPORATIONInventors: Swadesh Choudhary, Bahaa Fahim, Mahesh Wagh
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Patent number: 10846258Abstract: A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.Type: GrantFiled: September 30, 2016Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Venkatraman Iyer, Zuoguo Wu, Mahesh Wagh
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Publication number: 20200356436Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Publication number: 20200319957Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: ApplicationFiled: January 31, 2020Publication date: October 8, 2020Applicant: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Publication number: 20200320031Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.Type: ApplicationFiled: January 31, 2020Publication date: October 8, 2020Applicant: Intel CorporationInventors: Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
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Patent number: 10776302Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: GrantFiled: April 2, 2019Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20200244397Abstract: Data of different types are received on a plurality of data lanes of a physical link. Particular data is received on at least a portion of the plurality of data lanes, and a stream signal, corresponding to the particular data, is received on another of the lanes of the physical link, where the particular data is of a particular type different from other data previously sent on the plurality of data lanes. The stream signal includes a code component indicating that the particular data is of the particular type and a parity component for use in identifying whether a bit error is present in the stream signal.Type: ApplicationFiled: September 26, 2015Publication date: July 30, 2020Inventors: Venkatraman Iyer, Mahesh Wagh, Joon Teik HOR
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Publication number: 20200210366Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: ApplicationFiled: March 6, 2020Publication date: July 2, 2020Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
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Patent number: 10678736Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: September 25, 2015Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss