Abstract: A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to generate a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors having a first threshold voltage associated therewith and being operative to receive the first and second signals, respectively, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and operative to receive the difference signal and to generate an output signal of the circuit that is indicative of the difference signal and is referenced to the supply voltage of the circuit.

Abstract: A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.

Abstract: A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

Abstract: A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. An output stage is included in the comparator circuit for receiving the difference signal and for generating an output signal of the comparator circuit, the output signal being representative of the difference signal, the output stage having a switching point associated therewith. The comparator circuit further includes a voltage source coupled to the output of the differential amplifier. The voltage source is operative to generate a reference signal for establishing a common-mode voltage of the difference signal generated by the differential amplifier.

Abstract: A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.

Abstract: An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.

Abstract: A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.

Abstract: In one embodiment, the invention is a method for modeling electrical behavior of a packaged module having multiple integrated circuits (ICs), such as a multi-chip module (MCM). The method includes: (a) identifying one or more pin groups in the module, wherein a pin group comprises two or more buffers connected together and to a package-external pin, and (b) generating one or more corresponding unified behavioral models for the one or more pin groups based on the characteristics of the buffers of the one or more pin groups. The behavioral models are part of an integrated behavioral model file in accordance with the I/O buffer information specification (IBIS) standard.

Abstract: A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors operative to receive the first and second signals, respectively, each of the first and second transistors having a first threshold voltage associated therewith, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage.

Abstract: A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

Abstract: A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

Abstract: A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

Abstract: A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit.

Abstract: A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

Abstract: A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.

Abstract: A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.

Abstract: A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.

Abstract: A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.