Patents by Inventor Makiko Nakamura

Makiko Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100245961
    Abstract: An optical device includes: a movable plate disposed in an area over which externally incident light is spread, the movable plate having a light reflecting surface that reflects the light; and an axis member that swingably supports the movable plate around a predetermined axis, wherein each portion in the light spread area but other than the movable plate is formed of a surface having a normal vector along which the light is reflected and directed outside a predetermined area.
    Type: Application
    Filed: February 5, 2010
    Publication date: September 30, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yasushi MIZOGUCHI, Makiko NAKAMURA
  • Publication number: 20100238533
    Abstract: An optical device includes: an axis member including a plate-shaped attachment portion and an elastic support portion that swingably supports the attachment portion around a predetermined axis; a rigid member attached to one side of the attachment portion; and a light reflecting member attached to the other side of the attachment portion and having an area larger than that of the attachment portion.
    Type: Application
    Filed: January 28, 2010
    Publication date: September 23, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Makiko NAKAMURA, Yasushi MIZOGUCHI
  • Publication number: 20100046052
    Abstract: An actuator includes: a frame; first members at each end of the frame along a first axis making the frame rotatable thereabout; second members supporting each end of a movable plate against the frame along a second axis making the movable plate rotatable thereabout; first magnets with poles interposing the first axis; a second magnet with poles interposing the first axis; a coil generating a magnetic force acting on the first and second magnets; and a voltage source applying a voltage to the coil. The first and second magnets have an angle of 30-60 degrees to the first axis, and identical magnetic pole directions. The voltage source includes first and second voltage generators generating first and second voltages of first and second frequencies, and a voltage superimposer. The movable plate is rotated about the first and second axes at the first and second frequencies by the superimposed voltages.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 25, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yasushi MIZOGUCHI, Makiko NAKAMURA
  • Publication number: 20090231653
    Abstract: An optical deflector has: a movable plate having a reflecting surface and a side surface; and a support portion that supports the movable plate in such a manner that the movable plate is able to rotate around a predetermined axis, in which the side surface of the movable plate is recessed toward the axis.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 17, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Makiko NAKAMURA, Yasushi MIZOGUCHI
  • Publication number: 20090075415
    Abstract: The present invention provides a method for manufacturing a semiconductor device which has an integrated circuit provided on a semiconductor substrate and a movable part which is movable relative to the substrate. This manufacturing method includes: a step of covering the movable part with a sacrificial film; a step of covering the sacrificial film with a first sealing layer which is formed of a material having a tensile stress; a step of forming a through-hole in the first sealing layer; a step of removing the sacrificial film through the through-hole to form a void around the movable part; and a step of film-forming a second sealing layer on the first sealing layer to close the through-hole.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 19, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Makiko Nakamura
  • Publication number: 20080252942
    Abstract: An actuator includes a mass section; a support section; a coupling section for coupling the mass section rotatably to the support section so as to support the mass section with cantilever structure; and a pair of driving sources including a piezoelectric element for rotating the mass section, wherein the pair of driving sources are provided separately from each other with respect to a central axis of rotation of the mass section, each of the driving sources is provided slidably with respect to the coupling section or the support section, and the actuator is structured such that it causes the pair of piezoelectric elements to expand and contract in phases opposite to each other, so as to rotate at least a part of the coupling section while torsionally deforming the mass section.
    Type: Application
    Filed: September 7, 2007
    Publication date: October 16, 2008
    Applicant: Seiko Epson Corporation
    Inventors: Yasushi MIZOGUCHI, Mitsuhiro YODA, Makiko NAKAMURA
  • Publication number: 20080224319
    Abstract: A micro electro-mechanical system, which can be stably formed so as to prevent sticking of a movable part and which has a narrow gap, and a method of manufacturing the same are provided. The micro electro-mechanical system includes at least one fixed electrode formed above a principal surface of a semiconductor substrate and at least one movable electrode formed on the principal surface. The at least one movable electrode includes the movable part separated from the principal surface and the at least one fixed electrode. The movable part is movable with respect to the principal surface and the at least one fixed electrode.
    Type: Application
    Filed: October 26, 2007
    Publication date: September 18, 2008
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Publication number: 20080188025
    Abstract: A movable structural body formed over a semiconductor substrate is covered with a sacrifice film. The sacrifice film is covered with a silicon oxide film. Further, through holes are defined in the silicon oxide film. The sacrifice film is removed through the through holes to form space between the movable structural body and the silicon oxide film. Aluminum or an aluminum alloy high in flowability is deposited over the silicon oxide film by a sputtering method to seal the through holes.
    Type: Application
    Filed: December 18, 2007
    Publication date: August 7, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Makiko Nakamura
  • Patent number: 7176127
    Abstract: An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for forming the plug, based on a predetermined aspect ratio represented by a ratio of a depth dimension of the through hole to a diameter dimension of the through hole.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 13, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Patent number: 7049703
    Abstract: A semiconductor device includes a fine interconnection structure with low resistance at a through hole. A first interconnection is formed on a surface of a first layer insulating film. The first interconnection is tapered. An insulating layer is formed on the first interconnection and the first insulating film, and has a through hole that exposes an upper surface and a portion of a side surface of the first interconnection. The insulating layer covers a conductive portion of the first interconnection within the through hole. A second interconnection is provided over the insulating layer, and is electrically connected to the first interconnection through the through hole.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: May 23, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Publication number: 20050161831
    Abstract: An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for forming the plug, based on a predetermined aspect ratio represented by a ratio of a depth dimension of the through hole to a diameter dimension of the through hole.
    Type: Application
    Filed: March 18, 2005
    Publication date: July 28, 2005
    Inventor: Makiko Nakamura
  • Patent number: 6900131
    Abstract: The present invention provides a method of manufacturing a semiconductor device, which is capable of reducing variations in the rate of occurrence of failures at individual connecting portions in the semiconductor device. According to the semiconductor device manufacturing method, a Cu-containing TiN layer, which serves as a cap layer (130 (310)), is formed using a Cu-containing Ti target. Cu contained in the Cu-containing TiN layer is diffused into an Al—Cu wiring (120 (320)) located in a portion electrically connected to an interlayer wiring (200) by heat treatment.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: May 31, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Patent number: 6893960
    Abstract: A method for manufacturing a semiconductor device capable of forming a fine interconnection structure without making the resistance at the through hole high is provided. More specifically, a semiconductor device having a first interconnection formed on the surface of a first layer insulating film is provided, and a second interconnection is also provided on the upper part of the first interconnection and is electrically connected to the first interconnection, and wherein the first interconnection is formed so that the width of the lower part is narrower than that of the upper part.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: May 17, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Publication number: 20040198036
    Abstract: This invention provides a method for manufacturing a semiconductor device capable of forming a fine interconnection structure without making the resistance at the through hole high. More specifically, the present invention provides a semiconductor device having a first interconnection formed on the surface of a first layer insulating film and a second interconnection provided on the upper part of the first interconnection and electrically connected to the first interconnection, and wherein the first interconnection is formed so that the width of the lower part may become narrower than that of the upper part.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 7, 2004
    Inventor: Makiko Nakamura
  • Publication number: 20040130028
    Abstract: An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for forming the plug, based on a predetermined aspect ratio represented by a ratio of a depth dimension of the through hole to a diameter dimension of the through hole.
    Type: Application
    Filed: October 10, 2003
    Publication date: July 8, 2004
    Inventor: Makiko Nakamura
  • Publication number: 20040058524
    Abstract: The present invention provides a method of manufacturing a semiconductor device, which is capable of reducing variations in the rate of occurrence of failures at individual connecting portions in the semiconductor device. According to the semiconductor device manufacturing method, a Cu-containing TiN layer, which serves as a cap layer (130 (310)), is formed using a Cu-containing Ti target. Cu contained in the Cu-containing TiN layer is diffused into an Al—Cu wiring (120 (320)) located in a portion electrically connected to an interlayer wiring (200) by heat treatment.
    Type: Application
    Filed: April 30, 2003
    Publication date: March 25, 2004
    Inventor: Makiko Nakamura
  • Publication number: 20030036260
    Abstract: This invention provides a method for manufacturing a semiconductor device capable of forming a fine interconnection structure without making the resistance at the through hole high. More specifically, the present invention provides a semiconductor device having a first interconnection formed on the surface of a first layer insulating film and a second interconnection provided on the upper part of the first interconnection and electrically connected to the first interconnection, and wherein the first interconnection is formed so that the width of the lower part may become narrower than that of the upper part.
    Type: Application
    Filed: April 17, 2002
    Publication date: February 20, 2003
    Inventor: Makiko Nakamura
  • Patent number: 6475901
    Abstract: A semiconductor device including a semiconductor substrate, and a plurality of first interconnects formed over the semiconductor substrate. A first insulating layer covers the plurality of first interconnects, and a second insulating layer is formed between the plurality of first interconnects. The second insulating layer has substantially the same height as the plurality of first interconnects. An intermediate insulating layer is formed over the second insulating layer.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: November 5, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hidetomo Nishimura, Makiko Nakamura
  • Publication number: 20020072221
    Abstract: A semiconductor device includes a semiconductor substrate, and a plurality of first interconnects formed over the semiconductor substrate. A first insulating layer covers the plurality of first interconnects, and a second insulating layer is formed between the plurality of first interconnects. The second insulating layer has substantially the same height as the plurality of first interconnects. An intermediate insulating layer formed over the second insulating layer.
    Type: Application
    Filed: October 29, 2001
    Publication date: June 13, 2002
    Inventors: Hidetomo Nishimura, Makiko Nakamura
  • Patent number: 6368959
    Abstract: A first insulating film, a first wiring layer and a second insulating film are successively formed over a semiconductor substrate. A resist mask is patterned over the second insulating film, and isotropic etching and anisotropic etching are successively carried out to define a plurality of via holes within the second insulating film. The via holes thus have a first portion formed by the isotropic etching and a second portion formed by the anisotropic etching. The resist mask is removed, and a high melting-point metal film is formed over the second insulating film so as to be embedded in the plurality of via holes. The high melting-point metal film and the second insulating film are then polished down to the first portion of each of the via holes such that respective portions of the high melting-point metal film formed within adjacent ones of the plurality of via holes are isolated from each other.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: April 9, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura