Patents by Inventor Makiko Nakamura

Makiko Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6329719
    Abstract: A semiconductor device is comprised of a first wire that has a plurality of via holes formed in the vicinity of an end thereof and that is connected to a conductor of a different layer through the via holes, and a plurality of slits that are provided parallel to the direction in which the first wire extends and that split the first wire into a plurality of second wires over a predetermined distance from the end thereof.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: December 11, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Patent number: 6306762
    Abstract: A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is-formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: October 23, 2001
    Assignee: Electric Industry Co., Ltd.
    Inventors: Makiko Nakamura, Yasuhiro Fukuda, Yasuyuki Tatara, Yusuke Harada, Hiroshi Onoda
  • Patent number: 6288450
    Abstract: There is disclosed a wiring structure for a semiconductor device being excellent in the resistance against electromigration and being able to lengthen a life of the wiring. The wiring structure is comprised of a refractory metal layer and an aluminum alloy layer being stacked on the refractory metal layer. The wiring structure contains a compound layer produced between the refractory metal layer and the aluminum alloy layer. The refractory metal layer is parted in the extended direction of the wiring to prevent the compound layer produced between the refractory metal layer and the aluminum alloy layer from being ranged in the extended direction of the wiring. A length of an interval between the parted refractory metal layer portions is set to exceed a value being twice as large as a thickness of the compound layer. This prevents the compound layer growing between faces of refractory metal layer portion being opposite to each other being ranged each other.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: September 11, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Tadashi Narita, Makiko Nakamura
  • Patent number: 6166442
    Abstract: A semiconductor device is comprised of a first wire that has a plurality of via holes formed in the vicinity of an end thereof and that is connected to a conductor of a different layer through the via holes, and a plurality of slits that are provided parallel to the direction in which the first wire extends and that split the first wire into a plurality of second wires over a predetermined distance from the end thereof.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: December 26, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Patent number: 5646449
    Abstract: A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as DC magnetron sputtering, RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers.
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: July 8, 1997
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Makiko Nakamura, Yasuhiro Fukuda, Yasuyuki Tatara, Yusuke Harada, Hiroshi Onoda