Patents by Inventor Makoto Asai
Makoto Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140239313Abstract: A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming a buffer layer on a sapphire substrate, forming a Si-doped N+-layer with supplying silane, the N+-layer satisfying formula (Alx3Ga1-x3)y3In1-y3N, wherein 0?x3?1, 0?y3?1 and 0?x3+y3?1, forming an emission layer of a group III nitride compound semiconductor satisfying formula Alx1Gay1In1-x1-y1N, where 0?x1?1, 0?y1?1, and 0?x1+y1?1, on the N+-layer, and forming a P-layer of a P-type conduction on the emission layer, the P-layer including aluminum gallium nitride satisfying formula Alx2Ga1-x2N, wherein 0?x2?1.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: TOYODA GOSEI Co., LTD.Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
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Patent number: 8815701Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.Type: GrantFiled: July 11, 2012Date of Patent: August 26, 2014Assignee: Denso CorporationInventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
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Patent number: 8691635Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.Type: GrantFiled: July 25, 2012Date of Patent: April 8, 2014Assignees: Fuji Electric Co., Ltd., Denso CorporationInventors: Seiji Momota, Takeshi Fujii, Satoshi Kamijima, Makoto Asai
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Publication number: 20130009192Abstract: Provided is a nitride semiconductor light emitting device including p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer formed therebetween. A contact layer is positioned between the p-type nitride semiconductor layer and a p-side electrode. The contact layer includes a first p-type nitride layer having a first impurity concentration to form ohmic contact with the p-side electrode and a second p-type nitride layer having a second impurity concentration, the second impurity concentration having a concentration lower than the first impurity concentration.Type: ApplicationFiled: February 7, 2012Publication date: January 10, 2013Inventors: Hyun Wook Shim, Dong Ju Lee, Dong Ik Shin, Young Sun Kim, Makoto Asai, Yu Ri Sohn
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Publication number: 20120302036Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.Type: ApplicationFiled: July 11, 2012Publication date: November 29, 2012Applicant: DENSO CORPORATIONInventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
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Publication number: 20120289012Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.Type: ApplicationFiled: July 25, 2012Publication date: November 15, 2012Applicants: DENSO CORPORATION, FUJI ELECTRIC CO., LTD.Inventors: Seiji Momota, Takeshi Fujii, Satoshi Kamijima, Makoto Asai
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Patent number: 8278731Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.Type: GrantFiled: November 4, 2008Date of Patent: October 2, 2012Assignee: DENSO CORPORATIONInventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
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Publication number: 20120217510Abstract: A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming a high carrier concentration N+-layer satisfying the formula (Alx3Ga1-x3)y3In1-y3N, wherein 0?x3?1, 0?y3?1 and 0?x3+y3?1, forming an emission layer of a group III nitride compound semiconductor satisfying the formula, Alx1Gay1In1-x1-y1N, where 0?x1?1, 0?y1?1 and 0?x1+y1?1 on the high carrier concentration layer N+-layer, and forming a P-layer of a P-type conduction, on the emission layer, the P-layer including aluminum gallium nitride satisfying the formula Alx2Ga1-x2N, wherein 0?x2?1.Type: ApplicationFiled: May 10, 2012Publication date: August 30, 2012Applicant: Toyoda Gosei Co., Ltd.Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
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Patent number: 8253222Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.Type: GrantFiled: February 15, 2011Date of Patent: August 28, 2012Assignees: Fuji Electric Co., Ltd., Denso CorporationInventors: Seiji Momota, Takeshi Fujii, Satoshi Kamijima, Makoto Asai
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Patent number: 8097901Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.Type: GrantFiled: May 25, 2011Date of Patent: January 17, 2012Assignees: Denso Corporation, Fuji Electric Device Technology Co., Ltd.Inventors: Masaki Koyama, Yoshifumi Okabe, Makoto Asai, Takeshi Fujii, Koh Yoshikawa
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Publication number: 20110254051Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.Type: ApplicationFiled: June 28, 2011Publication date: October 20, 2011Applicant: DENSO CORPORATIONInventors: Yukio Tsuzuki, Makoto Asai
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Publication number: 20110220962Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.Type: ApplicationFiled: May 25, 2011Publication date: September 15, 2011Applicants: DENSO CORPORATION, Fuji Electric Device Technology Co., Ltd.Inventors: Masaki Koyama, Yoshifumi Okabe, Makoto Asai, Takeshi Fujii, Koh Yoshikawa
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Publication number: 20110204485Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.Type: ApplicationFiled: February 15, 2011Publication date: August 25, 2011Applicants: FUJI ELECTRIC SYSTEMS CO., LTD., DENSO CORPORATIONInventors: Seiji Momota, Takeshi Fujii, Satoshi Kamijima, Makoto Asai
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Patent number: 7999314Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.Type: GrantFiled: June 19, 2008Date of Patent: August 16, 2011Assignee: Denso CorporationInventors: Yukio Tsuzuki, Makoto Asai
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Patent number: 7977704Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.Type: GrantFiled: January 27, 2009Date of Patent: July 12, 2011Assignees: Denso Corporation, Fuji Electric Device Technology Co., Ltd.Inventors: Masaki Koyama, Yoshifumi Okabe, Makoto Asai, Takeshi Fujii, Koh Yoshikawa
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Publication number: 20110101412Abstract: A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming an N-layer of an N-type conduction, the N-layer comprising gallium nitride, forming a high carrier concentration N+-layer satisfying the formula (Alx3Ga1-x3)y3In1-y3N, wherein 0?x3?1, 0?y3?1 and 0?x3+y3?1, on the N-layer, forming an emission layer of a group III nitride compound semiconductor satisfying the formula, Alx1Gay1In1-x1-y1N, where 0?x1?1, 0?y1?1 and 0?x1+y1?1 on the high carrier concentration layer N+layer, doping Si and Zn into the emission layer, forming a P-layer of a P-type conduction, on the emission layer, the P-layer including aluminum gallium nitride satisfying the formula Alx2Ga1-x2N, wherein 0?x2?1, and forming a contact layer of a P-type conduction, on the P-type layer, the contact layer including gallium nitride.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Applicant: Toyoda Gosei Co., Ltd.Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
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Publication number: 20110012195Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).Type: ApplicationFiled: January 28, 2009Publication date: January 20, 2011Applicants: FUJI ELECTRIC SYSTEMS CO., LTD., DENSO CORPORATIONInventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
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Patent number: 7867800Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1?x3)y3In1?y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1?x2)y2In1?y2N emission layer (5), and a Mg-doped (Alx1Ga1?x1)y1In1?y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).Type: GrantFiled: December 20, 2007Date of Patent: January 11, 2011Assignee: Toyoda Gosei Co., Ltd.Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
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Patent number: 7838396Abstract: A semiconductor substrate is bonded to a joining face of a sheet and is dividable along predetermined dividing lines of the semiconductor substrate by expanding the sheet so as to form semiconductor chips. A bonding layer for bonding a substrate face of the semiconductor substrate and the joining face of the sheet to each other can be formed in each region encircled with the predetermined dividing lines, between the substrate face and the joining face of the sheet. Thus, when the substrate face of the semiconductor substrate and the joining face of the sheet are bonded to each other, the bonding layer does not reach any of the predetermined dividing lines set between the regions. The bonding layer can be formed in dotted segments or a pattern of lattice between the substrate face of the semiconductor substrate and the joining face of the sheet.Type: GrantFiled: November 9, 2006Date of Patent: November 23, 2010Assignee: Denso CorporationInventors: Yumi Maruyama, Makoto Asai
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Patent number: 7838331Abstract: A device separated from a wafer includes: a chip having a sidewall, which is provided by a dicing surface of the wafer in a case where the device is separated from the wafer; and a protection member disposed on the sidewall of the chip for protecting the chip from being contaminated by a dust from the dicing surface. In the device, the dicing surface of the wafer is covered with the protection member so that the chip is prevented from contaminated with the dust.Type: GrantFiled: November 14, 2006Date of Patent: November 23, 2010Assignee: Denso CorporationInventors: Atsushi Komura, Tetsuo Fujii, Muneo Tamura, Makoto Asai