Patents by Inventor Makoto Asai

Makoto Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060118821
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Application
    Filed: January 10, 2006
    Publication date: June 8, 2006
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Patent number: 7018915
    Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: March 28, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Toshiya Uemura, Makoto Asai, Yasuo Koide, Masanori Murakami
  • Patent number: 7015515
    Abstract: After one of layers constituting a superlattice structure is formed by an MOCVD method, NH3 gas is circulated together with H2 gas as a carrier gas to thereby perform a purge step. After the purge step, a next layer is formed.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: March 21, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Tetsuya Taki, Makoto Asai, Katsuhisa Sawazaki, Naoki Kaneyama, Toshiya Uemura
  • Patent number: 7001790
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 21, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Publication number: 20060008936
    Abstract: A method for manufacturing a semiconductor physical quantity sensor is provided. The sensor includes a multi-layered substrate, a cavity, a groove, a movable portion and a fixed portion. The multi-layered substrate includes a support substrate, an embedded insulation film, and a semiconductor layer. The method includes the steps of: preparing the multi-layered substrate having a sacrifice layer embedded in the semiconductor layer so that the sacrifice layer is disposed at a cavity-to-be-formed portion; forming the groove from the semiconductor layer to reach the sacrifice layer; and selectively etching the sacrifice layer from a bottom of the groove to form a cavity.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 12, 2006
    Inventor: Makoto Asai
  • Publication number: 20060008935
    Abstract: A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably supported on the substrate; and an insulation layer disposed on a bottom of the movable portion so that the insulation layer provides a roof of the cavity.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 12, 2006
    Inventor: Makoto Asai
  • Publication number: 20050229704
    Abstract: A semiconductor physical quantity sensor includes: a substrate; a semiconductor layer supported on the substrate; a trench disposed in the semiconductor layer; and a movable portion disposed in the semiconductor layer and separated from the substrate by the trench. The movable portion includes a plurality of through-holes, each of which penetrates the semiconductor layer in a thickness direction. The movable portion is capable of displacing on the basis of a physical quantity applied to the movable portion so that the physical quantity is detected by a displacement of the movable portion. The movable portion has a junction disposed among the through-holes. The junction has a trifurcate shape.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 20, 2005
    Inventors: Minoru Murata, Kenichi Yokoyama, Makoto Asai
  • Publication number: 20050224834
    Abstract: A light-emitting semiconductor device (10) consecutively includes a sapphire substrate (1), an AlN buffer layer (2), a silicon (Si) doped GaN n+-layer (3) of high carrier (n-type) concentration, a Si-doped (Alx3Ga1-x3)y3In1-y3N n+-layer (4) of high carrier (n-type) concentration, a zinc (Zn) and Si-doped (Alx2Ga1-x2)y2In1-y2N emission layer (5), and a Mg-doped (Alx1Ga1-x1)y1In1-y1N p-layer (6). The AlN layer (2) has a 500 ? thickness. The GaN n+-layer (3) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The n+-layer (4) has about a 2.0 ?m thickness and a 2×1018/cm3 electron concentration. The emission layer (5) has about a 0.5 ?m thickness. The p-layer 6 has about a 1.0 ?m thickness and a 2×1017/cm3 hole concentration. Nickel electrodes (7, 8) are connected to the p-layer (6) and n+-layer (4), respectively. A groove (9) electrically insulates the electrodes (7, 8).
    Type: Application
    Filed: June 3, 2005
    Publication date: October 13, 2005
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhide Manabe, Hisaki Kato, Michinari Sassa, Shiro Yamazaki, Makoto Asai, Naoki Shibata, Masayoshi Koike
  • Patent number: 6933169
    Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: August 23, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Makoto Asai
  • Patent number: 6861663
    Abstract: A buffer layer of aluminum nitride (AlN) about 25 nm thick is provided on a sapphire substrate. An n+ layer of a high carrier density, which is about 4.0 ?m thick and which is made of GaN doped with silicon (Si), is formed on the buffer layer. An intermediate layer of non-doped InxGa1?xN (0<x<1) about 3000 ? thick is formed on the high carrier density n+ layer. Then, an n-type clad layer of GaN about 250 ? thick is laminated on the intermediate layer. Further, three well layers of Ga0.8In0.2N about 30 ? thick each and two barrier layers of GaN about 70 ? thick each are laminated alternately on the n-type clad layer to thereby form a light-emitting layer of a structure with two multilayer quantum well (MQW) cycles.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: March 1, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Katsuhisa Sawazaki, Makoto Asai, Naoki Kaneyama
  • Publication number: 20040222499
    Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.
    Type: Application
    Filed: June 4, 2004
    Publication date: November 11, 2004
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Toshiya Uemura, Makoto Asai, Yasuo Koide, Masanori Murakami
  • Patent number: 6806571
    Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: October 19, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Toshiya Uemura, Makoto Asai, Yasuo Koide, Masanori Murakami
  • Publication number: 20040169192
    Abstract: A Group III nitride compound semiconductor layer 31 having a pit P is formed owing to a small region S (a). Temperature of a substrate is cooled down, supplying material and amount are switched, and then a second Group III nitride compound semiconductor layer 4 having larger aluminum compound is formed. By forming a layer having larger aluminum compound, the small region S which the first Group III nitride compound semiconductor layer 31 cannot cover is covered by the second Group III nitride compound semiconductor layer 4 (b). The bottom part S of the pit is covered by the second Group III nitride compound semiconductor layer 4 through lateral growth, and the first Group III nitride compound semiconductor layer 32 is grown again through epitaxial growth (c). Accordingly, the Group III nitride compound semiconductor layer 32 rapidly grows in a concave part, to thereby obtain a remarkably flat c-plane can be obtained (d).
    Type: Application
    Filed: March 3, 2004
    Publication date: September 2, 2004
    Inventors: Hisaki Kato, Makoto Asai, Naoki Kaneyama, Katsuhisa Sawazaki
  • Patent number: 6762070
    Abstract: A cap layer of GaN about 140 Å thick and a p-type clad layer of Mg-doped p-type AlxGa1-xN (x=0.12) about 200 Å thick are formed successively on an MQW active layer about 230 Å thick. A p-type contact layer of Mg-doped p-type AlyGa1-yN (y=0.05) about 600 Å thick is further formed thereon. These composition ratios x and y are selected to satisfy the expression “0.03≦0.3x≦y≦0.5x≦0.08”, so that the composition of the p-type contact layer becomes close to the composition of the p-type clad layer.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: July 13, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Kaneyama, Makoto Asai, Katsuhisa Sawazaki
  • Publication number: 20030155575
    Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 21, 2003
    Inventors: Naoki Shibata, Toshiya Uemura, Makoto Asai, Yasuo Koide, Masanori Murakami
  • Publication number: 20030122251
    Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.
    Type: Application
    Filed: February 24, 2003
    Publication date: July 3, 2003
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Makoto Asai
  • Patent number: 6573114
    Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: June 3, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Makoto Asai
  • Publication number: 20020197827
    Abstract: After one of layers constituting a superlattice structure is formed by an MOCVD method, NH3 gas is circulated together with H2 gas as a carrier gas to thereby perform a purge step. After the purge step, a next layer is formed.
    Type: Application
    Filed: June 7, 2002
    Publication date: December 26, 2002
    Inventors: Tetsuya Taki, Makoto Asai, Katsuhisa Sawazaki, Naoki Kaneyama, Toshiya Uemura
  • Publication number: 20020175332
    Abstract: A cap layer of GaN about 140 Å thick and a p-type clad layer of Mg-doped p-type AlxGa1-xN (x=0.12) about 200 Å thick are formed successively on an MQW active layer about 230 Å thick. A p-type contact layer of Mg-doped p-type AlyGa1-yN (y=0.05) about 600 Å thick is further formed thereon. These composition ratios x and y are selected to satisfy the expression “0.03≦0.3x≦y≦0.5x≦0.08”, so that the composition of the p-type contact layer becomes close to the composition of the p-type clad layer.
    Type: Application
    Filed: July 11, 2002
    Publication date: November 28, 2002
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Naoki Kaneyama, Makoto Asai, Katsuhisa Sawazaki
  • Patent number: 6452214
    Abstract: A cap layer of GaN about 140 Å thick and a p-type clad layer of Mg-doped p-type AlxGa1−xN (x=0.12) about 200 Å thick are formed successively on an MQW active layer about 230 Å thick. A p-type contact layer of Mg-doped p-type AlyGa1−yN (y=0.05) about 600 Å thick is further formed thereon. These composition ratios x and y are selected to satisfy the expression “0.03≦0.3x≦y≦0.5x≦0.08”, so that the composition of the p-type contact layer becomes close to the composition of the p-type clad layer.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: September 17, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Kaneyama, Makoto Asai, Katsuhisa Sawazaki