Abstract: An image forming system includes a transmitter apparatus that transmits, to a predetermined storage location of multiple storage locations, identification information identifying a user and image data associated with the identification information, and multiple image forming apparatuses. Each of the image forming apparatuses includes a first storage unit that stores storage information indicating the storage locations, a storage location that is included in the storage locations and stores the identification information and the image data associated with the identification information, a retrieval unit that accesses the storage locations, indicated by the storage information stored on the first storage unit, when the identification information is inputted by the user, and retrieves the image data from the storage location, and an image forming unit that forms an image corresponding to the image data retrieved by the retrieval unit.

Abstract: There are provided compounds having a superior PHD2 inhibitory effect that are represented by general formula (I?): (in the above-mentioned general formula (I?), W, Y, R2, R3, R4, and Y4 are as described hereinabove), or pharmaceutically acceptable salts thereof.

Abstract: Provided is an image reading apparatus including an image reading section that reads an image formed on a recording medium to generate image data, a display section that displays plural selection images that are registered in advance, used in selection of a storage destination of the generated image data, and an identifying section that identifies a user who stores the image data, wherein the display section displays, when the user is identified by the identifying section, the selection image corresponding to the identified user, and reduces a number of the selection images to be displayed to be less than a number of all the plural selection images to display the selection image.

Abstract: An image forming system includes a transmitter apparatus that transmits, to a predetermined storage location of multiple storage locations, identification information identifying a user and image data associated with the identification information, and multiple image forming apparatuses. Each of the image forming apparatuses includes a first storage unit that stores storage information indicating the storage locations, a storage location that is included in the storage locations and stores the identification information and the image data associated with the identification information, a retrieval unit that accesses the storage locations, indicated by the storage information stored on the first storage unit, when the identification information is inputted by the user, and retrieves the image data from the storage location, and an image forming unit that forms an image corresponding to the image data retrieved by the retrieval unit.

Abstract: An image forming system includes a transmitter apparatus that transmits, to a predetermined storage location of multiple storage locations, identification information identifying a user and image data associated with the identification information, and multiple image forming apparatuses. Each of the image forming apparatuses includes a first storage unit that stores storage information indicating the storage locations, a storage location that is included in the storage locations and stores the identification information and the image data associated with the identification information, a retrieval unit that accesses the storage locations, indicated by the storage information stored on the first storage unit, when the identification information is inputted by the user, and retrieves the image data from the storage location, and an image forming unit that forms an image corresponding to the image data retrieved by the retrieval unit.

Abstract: A shaft body (12) is rotatable around an axial line (C-C). A first valve element (13a) is located between a first opening (11a) and a second opening (11b) and it has a first notch (13a1). A second valve element (13b) is located between first opening (11a) and a third opening (11c) and it has a second notch (13b1). By rotating first and second valve elements (13a, 13b) around the axial line (C-C) as a center (O), an operation for opening and closing first and second notches (13a1, 13b1) can be performed.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data.

Abstract: According to one embodiment, a semiconductor storage device includes first cells, first bit and first word, and first sense. The first cells are capable of holding 2-level or higher-level data. The first bit and first word are capable of selecting the first cells. The first sense detects a first current. The first sense includes a first supply unit, a first accumulation unit, a detector, and a counter. The first supply unit supplies a second current when the data is read. The first accumulation unit accumulates an amount of charge. The detector detects the potential the amount of charge. The counter counts output from the detector. The counter includes a second supply unit, a second accumulation unit, and a sensing unit. The second supply unit charges a first node. The second accumulation unit accumulates a charge. The sensing unit detects the amount of charge of the second accumulation unit.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data.

Abstract: According to one embodiment, a semiconductor storage device includes a stripe, a sense amplifier, a global signal line, and a controller. Blocks are in the stripe. The blocks are formed in a first direction. Each of blocks is made a read unit of data and includes a memory cell capable of holding the data provided along a row and a column. The sense amplifier is provided just under each of the blocks, and reads the data. The global signal line is formed so as to penetrate through the stripe in the first direction, and transfers the data read from the block to the sense amplifier. The controller controls a value of a reference current applied to the sense amplifier according to positional relationship between each area in which the sense amplifier is arranged and the block, which is made a read target of the data, out of the blocks.

Abstract: According to one embodiment, a semiconductor storage device includes first cells, first bit and first word, and first sense. The first cells are capable of holding 2-level or higher-level data. The first bit and first word are capable of selecting the first cells. The first sense detects a first current. The first sense includes a first supply unit, a first accumulation unit, a detector, and a counter. The first supply unit supplies a second current when the data is read. The first accumulation unit accumulates an amount of charge. The detector detects the potential the amount of charge. The counter counts output from the detector. The counter includes a second supply unit, a second accumulation unit, and a sensing unit. The second supply unit charges a first node. The second accumulation unit accumulates a charge. The sensing unit detects the amount of charge of the second accumulation unit.

Abstract: An image forming system includes a transmitter apparatus that transmits, to a predetermined storage location of multiple storage locations, identification information identifying a user and image data associated with the identification information, and multiple image forming apparatuses. Each of the image forming apparatuses includes a first storage unit that stores storage information indicating the storage locations, a storage location that is included in the storage locations and stores the identification information and the image data associated with the identification information, a retrieval unit that accesses the storage locations, indicated by the storage information stored on the first storage unit, when the identification information is inputted by the user, and retrieves the image data from the storage location, and an image forming unit that forms an image corresponding to the image data retrieved by the retrieval unit.

Abstract: A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell.

Abstract: A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit selects the word lines. The voltage generator generates a first voltage and a second voltage lower than the first voltage. The first voltage is used by the first driver circuit to transfer a voltage to the unselected word line. The second voltage is used by circuits other than the first driver circuit.

Abstract: A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.

Abstract: A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.

Abstract: A semiconductor memory device includes a memory cell array, a first row decoder which drives the memory cell array, and a second row decoder which drives the memory cell array. The first and second row decoders simultaneously drive the memory cell array.

Abstract: A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having a plurality of word lines and a plurality of bit lines, and at least first and second page buffers to which the plurality of bit lines are connected. The plurality of word lines are divided into first and second word lines and the first and second word lines are arranged in positions corresponding to the at least first and second page buffers.