Abstract: A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon ca

Abstract: A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm3 and 5E+16 atoms/cm3 inclusive, and a thickness thereof is 8 ?m or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 ?m or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Abstract: A semiconductor rectifying device of an embodiment includes a first-conductive-type semiconductor substrate made of a wide bandgap semiconductor, a first-conductive-type semiconductor layer formed on an upper surface of the semiconductor substrate and made of the wide bandgap semiconductor having an impurity concentration lower than that of the semiconductor substrate, a first-conductive-type first semiconductor region formed at a surface of the semiconductor layer and made of the wide bandgap semiconductor, a second-conductive-type second semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor, a second-conductive-type third semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor having a junction depth deeper than a junction depth of the second semiconductor region, a first electrode that is formed on the first, second, and third semiconductor regions, and a second electrode formed on a lower surface of

Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.

Abstract: A wide bandgap semiconductor rectifying device of an embodiment includes a first-conductive-type wide bandgap semiconductor substrate and a first-conductive-type semiconductor layer that has an impurity concentration lower than that of the substrate. The device also includes a first-conductive-type first semiconductor region, and a second-conductive-type second semiconductor region that is formed between the first regions. The device also includes second-conductive-type third semiconductor regions in which at least part of the third regions are connected to the second wide bandgap semiconductor region, the third regions being formed between the first regions, the third regions having a width narrower than that of the second region. The device also includes a first electrode and a second electrode. In the device, a direction in which a longitudinal direction of the third regions are projected onto a (0001) plane of the layer has an angle of 90±30 degrees with respect to a <11-20> direction of the layer.

Abstract: According to one embodiment, a multi-dot flash memory includes an active area, a floating gate arranged on the active area via a gate insulating film and having a first side and a second side facing each other in a first direction, a word line arranged on the floating gate via an inter-electrode insulating film, a first bit line arranged on the first side of the floating gate via a first tunnel insulating film and extending in a second direction intersecting the first direction, and a second bit line arranged on the second side of the floating gate via a second tunnel insulating film and extending in the second direction. The active area has a width in the first direction narrower than that between a center of the first bit line and a center of the second bit line.

Abstract: A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.

Abstract: One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.

Abstract: A wide bandgap semiconductor rectifying device of an embodiment includes a first-conductive-type wide bandgap semiconductor substrate and a first-conductive-type semiconductor layer that has an impurity concentration lower than that of the substrate. The device also includes a first-conductive-type first semiconductor region, and a second-conductive-type second semiconductor region that is formed between the first regions. The device also includes second-conductive-type third semiconductor regions in which at least part of the third regions are connected to the second wide bandgap semiconductor region, the third regions being formed between the first regions, the third regions having a width narrower than that of the second region. The device also includes a first electrode and a second electrode. In the device, a direction in which a longitudinal direction of the third regions are projected onto a (0001) plane of the layer has an angle of 90±30 degrees with respect to a <11-20> direction of the layer.

Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.

Abstract: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

Abstract: A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

Abstract: A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a secon

Abstract: A semiconductor rectifier includes: a wide bandgap semiconductor substrate of a first conductivity type; a wide bandgap semiconductor layer of the first conductivity type which is formed on an upper surface of the wide bandgap semiconductor substrate and has an impurity concentration of 1E+14 atoms/cm3 or more and 5E+16 atoms/cm3 or less and a thickness of 20 ?m or more; a first wide bandgap semiconductor region of the first conductivity type formed on a surface of the wide bandgap semiconductor layer; a second wide bandgap semiconductor region of a second conductivity type formed to be sandwiched by the first wide bandgap semiconductor regions; a first electrode formed on the first and second wide bandgap semiconductor regions; and a second electrode formed on a lower surface of the wide bandgap semiconductor substrate, wherein a width of the second wide bandgap semiconductor region is 15 ?m or more.

Abstract: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

Abstract: According to one embodiment, a multi-dot flash memory includes an active area, a floating gate arranged on the active area via a gate insulating film and having a first side and a second side facing each other in a first direction, a word line arranged on the floating gate via an inter-electrode insulating film, a first bit line arranged on the first side of the floating gate via a first tunnel insulating film and extending in a second direction intersecting the first direction, and a second bit line arranged on the second side of the floating gate via a second tunnel insulating film and extending in the second direction. The active area has a width in the first direction narrower than that between a center of the first bit line and a center of the second bit line.