Abstract: A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.

Abstract: A semiconductor storing apparatus capable of shortening a ECC processing time of a readout operation is provided, including a flash memory includes: a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an error correcting code circuit receiving data from the page buffer/sense circuit and holding error address information of the data; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data of the data bus based on the error address information.

Abstract: A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).

Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a read only memory (ROM), a central processing unit, and a random access memory (RAM). The memory cell array stores data related to operating conditions of the semiconductor memory device. The ROM stores data used to control an operation of the semiconductor memory device. The central processing unit controls the operation of the semiconductor memory device according to the data read from the ROM. The central processing unit reads the data related to the operating conditions from the memory cell array in response to a requested operation and then temporarily stores the read data related to the operating conditions in the RAM. The central processing unit further reads the data related to the data related to the operating conditions from the RAM for controlling the operation of the semiconductor memory device.

Abstract: A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again.

Abstract: A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.

Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element determines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

Abstract: A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.

Abstract: A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again.

Abstract: A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.

Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element determines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element detennines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

Abstract: A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.

Abstract: A semiconductor memory device which is capable of high-speed operation in synchronization with external control signals is provided. The semiconductor memory device has a data input portion, a memory array, a data output portion, and a control portion. The data input portion receives command and address input data in response to the external control signals. The memory array has a plurality of memory elements. The data output portion outputs data read from the memory array in response to the external control signals. The control portion has the function of delay-compensation. During the time interval for receiving the input data, the function of delay-compensation estimates the delay time of the internal circuits, stores the estimated delay-time in a memory unit, and adjusts the output timing of the data output portion.

Abstract: A semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation are provided. The voltage generating circuit includes a plurality of registers A-1, B-1, C-1, D-1, voltage generating blocks A-2, B-2, C-2 and a voltage switch. The registers A-1, B-1, C-1, D-1 hold data provided from control logic. The voltage generating blocks A-2, B-2, C-2 generate voltage based on voltage control data held by the registers A-1, B-1, C-1. The voltage switch selects voltages based on selection control data held by the register D-1. The connecting element includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.

Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a read only memory (ROM), a central processing unit, and a random access memory (RAM). The memory cell array stores data related to operating conditions of the semiconductor memory device. The ROM stores data used to control an operation of the semiconductor memory device. The central processing unit controls the operation of the semiconductor memory device according to the data read from the ROM. The central processing unit reads the data related to the operating conditions from the memory cell array in response to a requested operation and then temporarily stores the read data related to the operating conditions in the RAM. The central processing unit further reads the data related to the data related to the operating conditions from the RAM for controlling the operation of the semiconductor memory device.

Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element detennines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.