Abstract: A voltage generating circuit 100 of the present invention includes a control logic 110, a voltage generating element 120 and a connecting element 130. The voltage generating element 120 includes a plurality of registers A-1, B-1, C-1, D-1, voltage generating blocks A-2, B-2, C-2 and a voltage switch 32. The registers A-1, B-1, C-1, D-1 hold data provided from control logic 110. The voltage generating blocks A-2, B-2, C-2 generate voltage based on voltage control data held by the registers A-1, B-1, C-1. The voltage switch 32 selects voltages based on selection control data held by the register D-1. The connecting element 130 includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.

Abstract: A semiconductor memory device for high speed operation, and for flexible data reading and programming is disclosed. The flash memory of the present disclosure includes: a page buffer/sensor circuit including a volatile memory element that may maintain data with a size corresponding to a page of a memory array; a high speed cache register including a non-volatile memory element that may maintain data with a size corresponding to a page of a memory array. The page buffer/sensor circuit includes a sensor circuit, a data register, and a transmission gate. The data register may transmit and receive data with an input-output buffer. The high speed cache register includes RRAM, wherein the RRAM may transmit and receive data with an input-output buffer via a transmission gate, and may transmit and receive data with the data register via a transmission gate.

Abstract: A reliable semiconductor memory device and an erasing method for erasing data in a reliable manner are provided. The erasing method is applied to erase a semiconductor memory device having a memory array, and the memory array has an NAND string. A predetermined voltage is applied to a gate of a select transistor of the NAND string, and the predetermined voltage is applied to a word line of a memory cell of the NAND string. An erasing voltage is applied to a substrate region at a first timing, and the substrate region has the NAND string. The gate of the select transistor is floated at a second timing. Here, there is a fixed time interval between the first timing and the second timing, and the second timing is later than the first timing.

Abstract: A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array. In the stage before an erasing pulse adding in an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data.

Abstract: A semiconductor memory device for high speed operation, and for flexible data reading and programming is disclosed. The flash memory of the present disclosure includes: a page buffer/sensor circuit including a volatile memory element that may maintain data with a size corresponding to a page of a memory array; a high speed cache register including a non-volatile memory element that may maintain data with a size corresponding to a page of a memory array. The page buffer/sensor circuit includes a sensor circuit, a data register, and a transmission gate. The data register may transmit and receive data with an input-output buffer. The high speed cache register includes RRAM, wherein the RRAM may transmit and receive data with an input-output buffer via a transmission gate, and may transmit and receive data with the data register via a transmission gate.

Abstract: A reliable semiconductor memory device and an erasing method for erasing data in a reliable manner are provided. The erasing method is applied to erase a semiconductor memory device having a memory array, and the memory array has an NAND string. A predetermined voltage is applied to a gate of a select transistor of the NAND string, and the predetermined voltage is applied to a word line of a memory cell of the NAND string. An erasing voltage is applied to a substrate region at a first timing, and the substrate region has the NAND string. The gate of the select transistor is floated at a second timing. Here, there is a fixed time interval between the first timing and the second timing, and the second timing is later than the first timing.

Abstract: TASK: to minimize variations of the threshold voltage distribution after programming and obtain a high-speed rewriting characteristic. MEANS FOR SOLVING THE PROBLEM: A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array, wherein before or after an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data.

Abstract: Disclosed is an eddy current flaw detection probe that is capable of pressing itself against an inspection target whose curvature varies. A flaw sensor is configured by fastening a plurality of coils to a flexible substrate that faces the surface of the inspection target. A first elastic body is positioned opposite the inspection target for the flaw sensor, is obtained by stacking two or more elastic plates, and has an elastic coefficient that varies in a longitudinal direction. A second elastic body is a porous body positioned between the flexible substrate and the first elastic body. A pressure section is employed to press the first elastic body toward the inspection target.

Abstract: Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.

Abstract: Disclosed is an eddy current flaw detection probe that is capable of pressing itself against an inspection target whose curvature varies. A flaw sensor is configured by fastening a plurality of coils to a flexible substrate that faces the surface of the inspection target. A first elastic body is positioned opposite the inspection target for the flaw sensor, is obtained by stacking two or more elastic plates, and has an elastic coefficient that varies in a longitudinal direction. A second elastic body is a porous body positioned between the flexible substrate and the first elastic body. A pressure section is employed to press the first elastic body toward the inspection target.

Abstract: Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.

Abstract: An ultrasonic inspection instrument for detecting a crack and performing sizing in the depth direction of the crack. By a transmitter element array and a receiver element array included in a common sensor, focus points between focused acoustic fields are electronically scanned in a range including a location where half the sum of the transmitting angle of ultrasonic waves to an inspection-target material and the receiving angle of diffraction echoes from the inspection-target material is 30 degrees, so that a tip portion of the crack is detected from the received diffraction echoes. Thus, the detectability of the ultrasonic inspection instrument for detecting diffraction waves in a subject to be inspected and performing crack inspection is stabilized and kept high.

Abstract: An ultrasonic inspection instrument for detecting a crack and performing sizing in the depth direction of the crack. By a transmitter element array and a receiver element array included in a common sensor, focus points between focused acoustic fields are electronically scanned in a range including a location where half the sum of the transmitting angle of ultrasonic waves to an inspection-target material and the receiving angle of diffraction echoes from the inspection-target material is 30 degrees, so that a tip portion of the crack is detected from the received diffraction echoes. Thus, the detectability of the ultrasonic inspection instrument for detecting diffraction waves in a subject to be inspected and performing crack inspection is stabilized and kept high.