Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: A method for using alkylsilane precursors during the sidewall formation process in MOS transistor fabrication processes. Alkylsilane precursors are used to form carbon contain silicon oxide layers (110) and carbon containing silicon nitride layers (120) during the sidewall formation process. The carbon containing layers (110) (120) introduce carbon into the extension regions (100) and the gate region (30) during thermal annealing.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: A method for using alkylsilane precursors during the sidewall formation process in MOS transistor fabrication processes. Alkylsilane precursors are used to form carbon contain silicon oxide layers (110) and carbon containing silicon nitride layers (120) during the sidewall formation process. The carbon containing layers (110) (120) introduce carbon into the extension regions (100) and the gate region (30) during thermal annealing.

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: A method for forming a high-k gate dielectric film (106) by CVD of a M-SiN or M-SION, such as HfSiO2. Post deposition anneals are used to adjust the nitrogen concentration.

Abstract: An economic and low thermal budget spacer is provided for both the cap oxide and nitride spacer is provided by amido-based silicon precursors such as BTBAS with an oxide to form the cap oxide and with same precursor and ammonia to form the nitride in a single wafer process.

Abstract: A sensor (1400) with radiation detectors (1421-1422) with two or more bolometer or photoconductor elements and bias polarity switching of one element to emulate mechanical chopping of input radiation. This electronic chopping permits higher chopping frequencies than mechanical chopping for bolometers because the scene settling time does not limit electronic chopping. The detectors may be within a single vacuum integrated circuit package with separate narrow passband filters for chemical spectral analysis.

Abstract: A room temperature emitter (10) operating in the 3-5 .mu.m wavelength range is provided. The emitter (10) includes a substrate (12) formed of a material selected from the group comprising cadmium telluride or cadmium zinc telluride. An epitaxial active layer (14) is formed over the substrate (12) from mercury cadmium telluride. The active layer (14) may be either a p-type or an n-type layer. The active layer (14) is doped with a predetermined concentration of dopant selected from the group comprising indium and arsenic. More particularly, if the active layer (14) is a p-type layer, it is doped with arsenic in a concentration between approximately 1.times.10.sup.16 atoms/cm.sup.3 and 1.times.10.sup.17 atoms/cm.sup.3. If the active layer (14) is an n-type layer, it is doped with indium in a concentration between approximately 5.times.10.sup.14 atoms/cm.sup.3 to 1.times.10.sup.15 atoms/cm.sup.3. A first epitaxial confinement layer (16) is formed from mercury cadmium telluride.

Abstract: In one embodiment, a semiconductor structure is disclosed. The structure includes both a silicon and a cadmium telluride layer. Each may have a (100) lattice orientation. A plurality of buffer layers are disposed between the silicon layer and the cadmium telluride layer. Each of these buffer layers has a lattice constant which is greater than the lattice constant of the layer below it and less than the lattice constant of the layer above it. As examples, these buffer layers may comprise zinc sulfide, zinc selenide, zinc telluride or zinc tellurium selenide.

Abstract: This is a sensor for, and a method of, determining if a particular type of flame is present, using at least two uncooled HgCdTe detector films on a common IR transmissive substrate. Specific examples of the types of radiation which can be identified include gasoline flames, natural gas flames, and organic combustion flames (identified, e.g., by comparing the amount of combined carbon dioxide and carbon monoxide to the amount of water vapor). The ratio of carbon dioxide to carbon monoxide can also be determined. The sensor can include a first HgCdTe filter (88) on a common IR transmissive substrate (42), a first uncooled HgCdTe detector film (86) over the first filter (88), and a second uncooled HgCdTe detector film (92) on a CdTe insulator which is either on the first uncooled HgCdTe detector film, or on a second HgCdTe filter (94) provided on the common IR transmissive substrate.

Abstract: In one embodiment, a semiconductor structure is disclosed. The structure includes both a silicon and a cadmium telluride layer. Each may have a (100) lattice orientation. A plurality of buffer layers are disposed between the silicon layer and the cadmium telluride layer. Each of these buffer layers has a lattice constant which is greater than the lattice constant of the layer below it and less than the lattice constant of the layer above it. As examples, these buffer layers may comprise zinc sulfide, zinc selenide, zinc telluride or zinc tellurium selenide.