Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.

Abstract: A CRC (cyclic redundancy check) generator circuit (28) generates a first CRC code based on a message. The CRC code is amended to the message, creating a first data packet. Circuitry transforms the first data packet to a second data packet for suitable transmission. Digital receiver circuitry receives the second data packet. A CRC verification circuit compares a received digital CRC code portion of the second data packet to a calculated digital CRC code portion. A message is presented for processing if no error is detected. A CRC-based FEC (forward error correction) circuit receives the message and calculates a digital CRC code from the verification circuit. When an error is detected, the detected error, based on a determination of whether the detected error affects an even number of bits or an odd number of bits, is corrected.

Abstract: A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction.

Abstract: Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory ; a low energy accelerator processor configured to execute instruction words coupled to the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).

Abstract: A wearable device is provided for authentication that includes a memory element and processing circuitry coupled to the memory element. The memory element configured to store a plurality of user profiles. The processing circuitry is configured to identify a pairing between the wearable device and a device. The processing circuitry is configured to identify a user of the wearable device. The processing circuitry also is configured to determine if the identified user matches a profile of the plurality of user profiles. The processing circuitry is also configured to responsive to the identified user matching the profile, determine if the profile provides authorization to access the device. The processing circuitry is also configured to responsive to the profile providing authorization to the device, send a message to the device authorizing access to the device.

Abstract: A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Abstract: A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Abstract: A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

Abstract: A communication system includes digital transmitter circuitry (26) including a CRC (cyclic redundancy check) generator circuit (28) generating a first CRC code based on a message and appending the CRC code to the message a first data packet, and circuitry (26-1,2,3) transforming the first data packet to provide a second data packet and transmitting it. Digital receiver circuitry (120) includes circuitry (12-1,2,3) receiving the second data packet, a CRC verification circuit (14-1) comparing a received digital CRC code portion of the second data packet to a calculated digital CRC code portion including any introduced error to detect the existence of any error in the second data packet.

Abstract: A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Abstract: A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

Abstract: A system, such as a computer aided design (CAD) system, is configured to abstract at least a portion of an integrated circuit (IC) design provided thereto. The system selects two signals of the IC and determines the respective sub-circuits ending at each of the signals, excluding the other sub-circuit when two sub-circuits intersect. It then identifies an intersection of the two sub-circuits and therefore establishes an abstraction therefrom. The abstraction replaces the circuit for verification purposes of the IC design. The process can repeat as may be necessary or until no two signals have sub-circuits that intersect. The process described for two signals is equally applicable to a plurality of signals for which the intersection is defined as the intersection of all the sub-circuits defined by the plurality signals. The abstraction allows for effective verification of portions of ICs as may be necessary.

Abstract: An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge message from a verifier. The challenge message has a challenge message frequency at a first challenge message frequency during a first time slot. The transmitter is configured to transmit a response message to the verifier. The response message has a response message frequency at a first response message frequency during the first time slot. The first response message frequency is different than the first challenge message frequency. The challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slit. The second challenge message frequency is different than the second response message frequency.

Abstract: A method for a processor computing a first trigonometric function to use an alternative trigonometric function for certain ranges of the operand. A modulo function may be used to provide an operand with a reduced range, and the modulo function may subtract in multiple steps in a manner that preserves low-order bits.

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract: A method for disparity cost computation for a stereoscopic image is provided that includes computing path matching costs for external paths of at least some boundary pixels of a tile of a base image of the stereoscopic image, wherein a boundary pixel is a pixel at a boundary between the tile and a neighboring tile in the base image, storing the path matching costs for the external paths, computing path matching costs for pixels in the tile, wherein the stored path matching costs for the external paths of the boundary pixels are used in computing some of the path matching costs of some of the pixels in the tile, and computing aggregated disparity costs for the pixels in the tile, wherein the path matching costs computed for each pixel are used to compute the aggregated disparity costs for the pixel.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: An embodiment of the invention provides a cryptographic device that draws a substantially constant current from an accessible electrical node that supplies power to the cryptographic device. Keeping the current drawn from the accessible electrical node substantially constant reduces the probability that secure information may be taken by unwanted third parties from the cryptographic device. The cryptographic device includes an active shunt current regulator, a low-pass filter, a linear voltage regulator and an AES (advanced encryption standard) circuit.