Abstract: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.

Abstract: A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.

Abstract: A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.

Abstract: A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.

Abstract: A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.

Abstract: A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes.

Abstract: A communication system includes a receiver configured to receive a packet that contains plural codewords, and a codeword failure detector cooperatively operable with the receiver. The codeword failure detector can be configured to detect a codeword failure in at least one codeword of the plural codewords as it is being received by the receiver, and to terminate reception at the receiver, when the codeword failure is detected before the end of the packet, to put the receiver into a power save mode for a duration of a remainder of the packet that contains the at least one codeword.

Abstract: In some embodiments, a device includes a multiple-input multiple-output (“MIMO”) decoder module coupled to a first log-likelihood-ratio (“LLR”) computing unit. The decoder module includes at least one processing unit and at least one sorting unit. The decoder module preferably uses a K-best breadth-first search method to decode data from MIMO sources. In some embodiments, a method includes receiving data representing a vector of receive signal samples detected by multiple receive transceivers. The method further includes performing a K-best breadth-first search on the data to obtain an estimated constellation point. The method further includes providing a user data stream based at least in part on the estimated constellation point.

Abstract: The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files.

Abstract: In at least some embodiments, a method is provided. The method includes receiving samples from a first input channel and a second input channel. The method further includes controlling commutators to selectively switch samples between the first and second input channels for input to a radix-2 butterfly. The method further includes continuously activating the radix-2 butterfly while processing samples received from the first input channel followed by samples received from the second input channel.

Abstract: The present invention provides a packet detector for use with a packet-based wireless receiver employing a receive antenna for P concurrently transmitted streams, where P is at least two. In one embodiment, the packet detector includes a correlation unit coupled to the single receive antenna and configured to provide a correlation function based on P acquisition fields corresponding to the P concurrently transmitted streams. Additionally, the packet detector also includes a pseudo-magnitude calculator coupled to the correlation unit and configured to calculate a packet detection metric based on the correlation function.

Abstract: In MIMO wireless communications employing LMMSE receiver, the symbols transmitted through a transmit antenna are estimated at the receiver in the presence of interference consisting of two main components: one due to the additive noise and the other due to (interfering) symbols transmitted via the remaining antennas. This has been shown to hamper the performance of a communication system resulting in incorrect symbol decisions, particularly at low SNR. IMMSE has been devised as a solution to cope with this problem; In IMMSE processing, the symbols sent via each transmit antenna are decoded iteratively. In each stage of processing, the received signal is updated by removing the contribution of symbols detected in the previous iterations. In principle, this reduces the additive interference in which the desired symbols are embedded in. Therefore, the interference level should reduce monotonically as one goes down in processing order.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

Abstract: A system includes a Viterbi decoder. The Viterbi decoder includes add compare select logic. The add compare select logic determines path metrics for an encoded signal. The add compare select logic also is shared to determine a best state by which trace-back procedure gets started, resulting in hardware saving.

Abstract: A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.

Abstract: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.

Abstract: A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic interconnecting at least some of the adaptive equalizers, and a control mechanism that, according to different MDPEs, configures at least some of the adaptive equalizers and control logic.

Abstract: A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.

Abstract: A device and a method of characterizing a communications channel. The method includes transmitting a first part of a packet preamble using two or more antennas and transmitting a second part of the packet preamble using the two or more antennas. Each antenna transmits an orthogonal encoding of the second part of the packet preamble. The method also includes transmitting a packet header using the two or more antennas and transmitting a packet payload using the two or more antennas. Each antenna transmits an orthogonal encoding of the packet header. The packet payload may be encoded across the transmissions of the two or more antennas.