Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract: In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract: A method and apparatus for parameter-based sensor selection is disclosed. In one embodiment, a system includes an integrated circuit (IC) having a first power management circuit, and a second power management circuit external to the IC. The IC includes various functional units implemented in various power domains, while the second power management circuit (which may be implemented on an IC) includes a number of voltage regulators for providing power to the power domains. The second power management circuit also includes sensors that provide data about a system parameter, with the data being provided at telemetry to the first power management circuit. When the system parameter is less than a first threshold, the telemetry data may be based on a first sensor. When the system parameter is greater than the first threshold, the telemetry data may be based on a second sensor.

Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.

Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.

Abstract: In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.

Abstract: A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.

Abstract: In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.

Abstract: A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.