Abstract: In a processing system, when a processing device of the processing system is configured to transceive packets in a bridge mode, the processing device inserts packets into upstream packet traffic (i.e., traffic destined for the host) in accordance with a 1st bandwidth allocation policy. When the processing device is configured in a tunnel-bridge hybrid mode, the processing device determines upstream loading from downstream processing devices. The processing device then inserts packets into the upstream packet traffic in accordance with a 2nd bandwidth allocation policy based on the upstream loading.

Abstract: According to the present invention, the multiple processor device determines routing for a plurality of data segments. In determining the routing, the multiple processor device first receives the plurality of data segments. The plurality of data segments include multiplexed data fragments from at least one of a plurality of virtual channels. Further, a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The multiple processor device then applies at least one routing rule to one of the plurality of data segments to produce at least one result corresponding to the one of the plurality of data segments. The multiple processor device then interprets the at least one result to determine whether sufficient information is available to render a routing decision for the one of the plurality of data segments.

Abstract: A multiple processor device schedules data from at least one of a plurality of virtual channels for transmission during a 1st transmission cycle. The multiple processor device then determines a storage location for the data of the virtual channel during a 2nd transmission cycle to produce a determined storage location. The multiple processor device then stores the data of the virtual channel in the determined storage location during a 3rd transmission cycle. The multiple processor device then packetizes, during a 4th transmission cycle, the stored data in accordance with a 1st or 2nd transmission protocol (e.g., HT, SPI, et cetera) to produce a packetized transmission.

Abstract: A multiple processor integrated circuit includes a plurality of processing units, cache memory, a memory controller, an internal bus, a packet manager, a node controller, configurable packet-based interfaces, and a switching module. The internal bus couples the plurality of processing units, the cache memory, the memory controller, the packet manager, and the node controller together. The switching module couples the configurable packet-based interfaces with the packet manager and node controller. Each of the packet-based interfaces may be configured to provide a tunnel function, a bridge function, and/or a tunnel-bridge hybrid function. In the tunnel-bridge hybrid mode, the packet-based interfaces enable the multiple processor integrated circuit to provide peer-to-peer communication with other multiple processor integrated circuits in a processing system that includes a plurality of multiple processor ICs.

Abstract: Smart routing between peers in a point-to-point link based system begins when a device of a plurality of devices in a point-to-point link interconnected system receives a packet from an upstream link or a downstream link. The processing continues when the device interprets the packet to determine a destination of the packet. If the device is the destination of the packet, the device accepts the packet. If, however, the device is not the destination of the packet, the device forwards the packet on another upstream link or another downstream link without alteration of at least one of: source information of the packet and destination information of the packet.

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract: An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Abstract: An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

Abstract: A multiplier capable of performing complex iterative calculations such as division and square root concurrently with simple independent multiplication operations is disclosed. The division and square root operations are performed using iterative multiplication operations such as the Newton Raphson iteration and series expansion. These iterative calculations may require a number of passes through the multiplier. Since the multiplier may be pipelined, it may experience a number of idle cycles during the iterative calculations. The multiplier is configured to utilize these idle cycles to perform independent simple multiplication operations. The multiplier may be configured to assert a control signal that is indicative of future idle cycles in the first stages of the multiplier pipeline. The control signal may be used by control logic to dispatch independent simple multiplication operations to the multiplier for execution during the idle clock cycles.