Abstract: In an approach to improve resolving defects within computer hardware, programs, software, or systems, embodiments pause mainline traffic and isolating interface or retention issues, and determine one or more types of errors in an event of a mainline traffic fail, wherein debug techniques are applied to fail information to resolve or further diagnose the one or more types of errors, and wherein the debug techniques are tracked and categorized. Additionally, embodiments apply corrective read actions to a detected error based on previously stored corrective actions associated with the detected error, and responsive to identifying no additional actions are required, restoring a collected system data. Further, embodiments, resume the paused mainline traffic.

Abstract: In an approach to improve resolving defects within computer hardware, programs, software, or systems, embodiments pause mainline traffic and isolating interface or retention issues, and determine one or more types of errors in an event of a mainline traffic fail, wherein debug techniques are applied to fail information to resolve or further diagnose the one or more types of errors, and wherein the debug techniques are tracked and categorized. Additionally, embodiments apply corrective read actions to a detected error based on previously stored corrective actions associated with the detected error, and responsive to identifying no additional actions are required, restoring a collected system data. Further, embodiments, resume the paused mainline traffic.

Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.

Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

Abstract: An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Abstract: Aspects of the invention include fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory. An error status of the data fetched from the primary memory is determined. The error status is one of correctable error (CE), uncorrectable error (UE), and no error. Based at least in part on determining that the data fetched from the primary memory has the error status of no error, the data fetched from the primary memory is output to the requestor. Based at least in part on determining that the data fetched from the primary memory has the error status of UE or CE, the data requested by the requestor is fetched from the secondary memory.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.

Abstract: Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.

Abstract: Confirming memory marks indicating an error in computer memory including detecting, by memory logic responsive to a memory read operation, an error in at a memory location; marking, by the memory logic in an entry in a hardware mark table, the memory location as containing the error, the entry including one or more parameters for correcting the error; and retrying, by the memory logic, the memory read operation, including: responsive to again detecting the error in the memory location, determining whether the error is correctable at the memory location using the parameters included in the entry; and if the error is correctable at the memory location using the one or more parameters included in the entry, confirming the error in the entry of the hardware mark table.

Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.

Abstract: A Local Timer Engine (LTE) is disclosed. For an initiator in a computing system, the LTE measures a respective time delay for each of a plurality of routes between the initiator and a plurality of destinations. For each of the plurality of routes, the LTE determines a respective timeout value based on the measured respective time delay for the route and determines a unique memory mapped address identifying the route. The initiator sends a request to the LTE for a timeout value. The LTE determines a proper timeout value and provides the proper timeout value to the initiator.

Abstract: Aspects of the invention include fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory. An error status of the data fetched from the primary memory is determined. The error status is one of correctable error (CE), uncorrectable error (UE), and no error. Based at least in part on determining that the data fetched from the primary memory has the error status of no error, the data fetched from the primary memory is output to the requestor. Based at least in part on determining that the data fetched from the primary memory has the error status of UE or CE, the data requested by the requestor is fetched from the secondary memory.