Abstract: A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.

Abstract: Determining an underlying cause for errors that are detected in the data processing system is performed. An occurrence of at least one error in the data processing system is detected, thereby forming a detected error. Responsive to detecting the detected error, a determination is made as to whether there is at least one previously recorded error in an error history data structure that is the underlying cause for the detected error. The at least one previously recorded error is related to the detected error and the at least one previously recorded error is of a different type from the detected error. Responsive to identifying the at least one previously recorded error, the at least one previously recorded error is reported to a user.

Abstract: A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: Determining an underlying cause for errors that are detected in the data processing system is performed. An occurrence of at least one error in the data processing system is detected, thereby forming a detected error. Responsive to detecting the detected error, a determination is made as to whether there is at least one previously recorded error in an error history data structure that is the underlying cause for the detected error. The at least one previously recorded error is related to the detected error and the at least one previously recorded error is of a different type from the detected error. Responsive to identifying the at least one previously recorded error, the at least one previously recorded error is reported to a user.

Abstract: A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions.

Abstract: A computer implemented method, apparatus, and computer usable program code for performing a diagnostic in a hardware component established in a data processing system. The method includes starting a first slow mode initial program loading in the hardware component, wherein the hardware component contains a first diagnostic routine. A determination is made whether the first diagnostic routine fails during the slow mode initial program loading. Responsive to a determination that the first diagnostic routine fails, the first diagnostic routine is isolated.

Abstract: A method, apparatus, and computer program product are disclosed for enhancing the error reporting that is done utilizing fault isolation registers (FIRs) after executing a diagnostic test. A diagnostic test is generated that will test for a particular type of error. A particular FIR is designated to be used to report the particular type of error. The particular FIR is designated in the design of the particular diagnostic test and the design of the particular FIR. Another FIR that is not designed to be used to report the particular type of error is also selected. This other FIR is unrelated to the diagnostic test. The result of the execution of the diagnostic test is reported utilizing the particular FIR and the other, selected FIR.