Patents by Inventor Marie Denison
Marie Denison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495580Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: GrantFiled: November 8, 2018Date of Patent: November 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Publication number: 20220052195Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.Type: ApplicationFiled: November 1, 2021Publication date: February 17, 2022Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
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Patent number: 11189721Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.Type: GrantFiled: August 17, 2020Date of Patent: November 30, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Sameer Pendharkar, Guru Mathur
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Patent number: 11152459Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.Type: GrantFiled: January 7, 2020Date of Patent: October 19, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Philip L. Hower, Sameer Pendharkar
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Publication number: 20200381552Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
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Patent number: 10811530Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.Type: GrantFiled: June 30, 2017Date of Patent: October 20, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Sameer Pendharkar, Guru Mathur
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Publication number: 20200146945Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.Type: ApplicationFiled: January 7, 2020Publication date: May 14, 2020Inventors: Marie DENISON, Philip L. HOWER, Sameer PENDHARKAR
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Patent number: 10535731Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.Type: GrantFiled: April 17, 2018Date of Patent: January 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Philip L. Hower, Sameer Pendharkar
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Patent number: 10468324Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.Type: GrantFiled: June 16, 2016Date of Patent: November 5, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Archana Venugopal, Marie Denison, Luigi Colombo, Sameer Pendharkar
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Publication number: 20190088628Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: ApplicationFiled: November 8, 2018Publication date: March 21, 2019Inventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Patent number: 10128219Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: GrantFiled: April 25, 2013Date of Patent: November 13, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Patent number: 10062777Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.Type: GrantFiled: April 12, 2017Date of Patent: August 28, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Sameer Pendharkar, Guru Mathur
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Publication number: 20180240870Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.Type: ApplicationFiled: April 17, 2018Publication date: August 23, 2018Inventors: Marie DENISON, Philip L. HOWER, Sameer PENDHARKAR
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Patent number: 9985095Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.Type: GrantFiled: June 15, 2016Date of Patent: May 29, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Philip L. Hower, Sameer Pendharkar
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Patent number: 9947784Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.Type: GrantFiled: November 30, 2016Date of Patent: April 17, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
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Publication number: 20170373184Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.Type: ApplicationFiled: June 30, 2017Publication date: December 28, 2017Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
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Patent number: 9831320Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.Type: GrantFiled: February 2, 2016Date of Patent: November 28, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
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Patent number: 9806190Abstract: An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).Type: GrantFiled: October 26, 2011Date of Patent: October 31, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Philip L. Hower, Sameer Pendharkar
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Patent number: 9793375Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.Type: GrantFiled: February 2, 2016Date of Patent: October 17, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
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Publication number: 20170222040Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.Type: ApplicationFiled: April 12, 2017Publication date: August 3, 2017Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR