Patents by Inventor Mariko Iizuka
Mariko Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11710531Abstract: Memories, and their operation, might include a plurality of content addressable memory (CAM) cells each for storing a respective data value, a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value, and a plurality of storage elements each for storing a respective data value, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to generate a data signal indicative of the respective data value of that storage element if a match of their corresponding CAM cells is indicated.Type: GrantFiled: December 3, 2020Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventor: Mariko Iizuka
-
Publication number: 20210202024Abstract: Memories, and their operation, might include a plurality of content addressable memory (CAM) cells each for storing a respective data value, a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value, and a plurality of storage elements each for storing a respective data value, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to generate a data signal indicative of the respective data value of that storage element if a match of their corresponding CAM cells is indicated.Type: ApplicationFiled: December 3, 2020Publication date: July 1, 2021Applicant: MICRON TECHNOLOGY, INC.Inventor: Mariko Iizuka
-
Patent number: 9704918Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.Type: GrantFiled: February 19, 2016Date of Patent: July 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi Miyakawa, Katsuhiko Hoya, Mariko Iizuka, Takashi Nakazawa, Hiroyuki Takenaka
-
Patent number: 9552861Abstract: A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.Type: GrantFiled: February 9, 2016Date of Patent: January 24, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mariko Iizuka, Kosuke Hatsuda
-
Publication number: 20160197120Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.Type: ApplicationFiled: February 19, 2016Publication date: July 7, 2016Inventors: Tadashi MIYAKAWA, Katsuhiko HOYA, Mariko IIZUKA, Takashi NAKAZAWA, Hiroyuki TAKENAKA
-
Patent number: 9368199Abstract: A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.Type: GrantFiled: December 15, 2014Date of Patent: June 14, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi Miyakawa, Katsuhiko Hoya, Mariko Iizuka, Hiroyuki Takenaka
-
Publication number: 20160155486Abstract: A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.Type: ApplicationFiled: February 9, 2016Publication date: June 2, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mariko IIZUKA, Kosuke HATSUDA
-
Patent number: 9293171Abstract: According to one embodiment, first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.Type: GrantFiled: September 10, 2014Date of Patent: March 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mariko Iizuka, Kosuke Hatsuda
-
Publication number: 20160064073Abstract: A resistance change type memory device according to an embodiment includes a plurality of memory elements; a first to a fourth bit lines connected to the plurality of memory elements, respectively; a first to a fourth transistors connected at their one ends to the first to the fourth bit lines, respectively; a fifth transistor connected at its one end to the other ends of the first and second transistors; a sixth transistor connected at its one end to the other ends of the third and fourth transistors; and a fifth bit line connected to the other ends of the fifth and sixth transistors.Type: ApplicationFiled: December 23, 2014Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nao MATSUOKA, Kosuke HATSUDA, Mariko IIZUKA, Katsuhiko HOYA, Hiroyuki TAKENAKA
-
Publication number: 20160064075Abstract: A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.Type: ApplicationFiled: December 15, 2014Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tadashi MIYAKAWA, Katsuhiko HOYA, Mariko IIZUKA, Hiroyuki TAKENAKA
-
Patent number: 9251918Abstract: A semiconductor memory device includes: a bank including a normal area including normal columns, and a redundancy area including redundancy columns and to be replaced with a failure column of the normal area; sense amplifiers connected to the normal area; and a redundancy sense amplifier connected to the redundancy area. A normal replacement unit is formed of normal columns allocated to each of the sense amplifiers. A redundancy replacement unit is formed of redundancy columns allocated to the redundancy sense amplifier. The redundancy replacement unit is smaller than the normal replacement unit.Type: GrantFiled: March 5, 2014Date of Patent: February 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Mariko Iizuka
-
Publication number: 20150262622Abstract: According to one embodiment, first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.Type: ApplicationFiled: September 10, 2014Publication date: September 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mariko IIZUKA, Kosuke HATSUDA
-
Publication number: 20150070982Abstract: According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.Type: ApplicationFiled: March 7, 2014Publication date: March 12, 2015Inventors: Tadashi MIYAKAWA, Katsuhiko HOYA, Mariko IIZUKA, Takashi NAKAZAWA, Hiroyuki TAKENAKA
-
Publication number: 20150063013Abstract: A semiconductor memory device includes: a bank including a normal area including normal columns, and a redundancy area including redundancy columns and to be replaced with a failure column of the normal area; sense amplifiers connected to the normal area; and a redundancy sense amplifier connected to the redundancy area. A normal replacement unit is formed of normal columns allocated to each of the sense amplifiers. A redundancy replacement unit is formed of redundancy columns allocated to the redundancy sense amplifier. The redundancy replacement unit is smaller than the normal replacement unit.Type: ApplicationFiled: March 5, 2014Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mariko IIZUKA
-
Patent number: 8837240Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.Type: GrantFiled: September 14, 2012Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Iwai, Makoto Takahashi, Masaharu Wada, Mariko Iizuka, Kimimasa Imai
-
Patent number: 8675431Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.Type: GrantFiled: March 20, 2012Date of Patent: March 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Iwai, Makoto Takahashi, Masaharu Wada, Mariko Iizuka, Kimimasa Imai
-
Patent number: 8625384Abstract: A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line.Type: GrantFiled: March 22, 2011Date of Patent: January 7, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Mariko Iizuka
-
Publication number: 20130077420Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.Type: ApplicationFiled: September 14, 2012Publication date: March 28, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayuki Iwai, Makoto Takahashi, Masaharu Wada, Mariko Iizuka, Kimimasa Imai
-
Publication number: 20130051167Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.Type: ApplicationFiled: March 20, 2012Publication date: February 28, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayuki Iwai, Makoto Takahashi, Masaharu Wada, Mariko Iizuka, Kimimasa Imai
-
Patent number: D664645Type: GrantFiled: September 7, 2011Date of Patent: July 31, 2012Assignee: The Procter & Gamble CompanyInventors: Signe Christina Larson, Naomi Ruth Nelson, Mariko Iizuka