Abstract: A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line.

Abstract: A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

Abstract: A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

Abstract: A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

Abstract: A semiconductor storage device includes a normal area that contains a plurality of memory cells and a redundancy area that contains a plurality of memory cells. The semiconductor storage device further includes a delaying unit that changes, between a first mode in which both the normal area and the redundancy area are used and a second mode in which only the normal area is used without use of the redundancy area, a timing for issuing a cell-array control signal for selecting a memory cell from among the memory cells used in a corresponding mode.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit operative to change in the storage capacity of the memory cell array and change in the address space required for access to the memory cell based on a control signal.

Abstract: A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

Abstract: A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer block connected to the first memory block via first complementary data lines and connected to the second memory block via second complementary data lines. It also includes a dynamic data shift redundancy circuit block connected to the DQ buffer block via local data lines and operative to relieve the first and second memory blocks.

Abstract: A semiconductor memory device includes an interface unit connected to an external circuit, a data memory unit including a write data line, a read-out data line, a data control unit, and a memory block connected to the data control unit, and a read-out latch block connected between a read-out data line and the interface unit. The data control unit outputs data read out of the memory block to the read-out data line with a trailing edge of a clock being used as a trigger. The read-out latch block latches the data with a trailing edge of another clock, which is generated at least one cycle after the trailing edge of the aforementioned clock, being used as a trigger. The interface unit outputs the data to the external circuit with a leading edge of still another clock, which follows the aforementioned another clock, being used as a trigger.

Abstract: A glycosidase inhibitor comprising as an active ingredient an extract of Ascophyllum nodosum which is a kind of brown algae can be used as a useful healthy food or food for specified health uses for the treatment and/or prevention of diabetes.

Abstract: A lipase inhibitor comprising as an active ingredient an extract of Ascophyllum nodosum which is a kind of brown algae can be used as a useful healthy food or food for specified health uses for the treatment and/or prevention of obesity or hyperlipemia.

Abstract: A semiconductor memory device includes an interface unit connected to an external circuit, a data memory unit including a write data line, a read-out data line, a data control unit, and a memory block connected to the data control unit, and a read-out latch block connected between a read-out data line and the interface unit. The data control unit outputs data read out of the memory block to the read-out data line with a trailing edge of a clock being used as a trigger. The read-out latch block latches the data with a trailing edge of another clock, which is generated at least one cycle after the trailing edge of the aforementioned clock, being used as a trigger. The interface unit outputs the data to the external circuit with a leading edge of still another clock, which follows the aforementioned another clock, being used as a trigger.